NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 87

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5
Warning:
Table 5-1.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host-PCI Express Bridge
Registers (D1:F0)
Device 1 contains the controls associated with the PCI Express root port. In addition, it
also functions as the virtual PCI-to-PCI bridge.
the D1:F0 registers listed by address offset in ascending order.
detailed bit description of the registers.
When reading the PCI Express “conceptual” registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express Specification defines two types of reserved bits: Reserved and
Preserved:
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
It is important to note that most (if not all) control bits in this device cannot be
modified unless the link is down. Software is required to first Disable the link, then
program the registers, and then re-enable the link (which will cause a full-retrain with
the new settings).
Host-PCI Express Bridge Register Address Map (D1:F0) (Sheet 1 of 3)
1. Reserved for future RW implementations; software must preserve value read for
2. Reserved and Zero: Reserved for future R/WC/S implementations; software must
Address
09-0Bh
00-01h
02-03h
04-05h
06-07h
0F-17h
Offset
0Dh
1Dh
08h
0Ch
0Eh
18h
19h
1Ah
1Bh
1Ch
writes to bits.
use 0 for writes to bits.
Register Symbol
SUBUSN1
PCICMD1
IOLIMIT1
IOBASE1
PCISTS1
SBUSN1
PBUSN1
HDR1
DID1
VID1
RID1
CC1
CL1
—
—
—
Cache Line Size
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Reserved
Header Type
Reserved
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Reserved
I/O Base Address
I/O Limit Address
Register Name
Table 5-1
provides an address map of
Default Value
060400h
8086h
2779h
0000h
0010h
Section 5.1
C0h
00h
01h
00h
00h
00h
F0h
00h
—
—
—
provides a
RO, R/WC
RO, R/W
Access
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
—
—
—
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