NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 109

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
Note:
5.1.38
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
The error reporting bits are in reference to errors detected by this device, not errors
messages received across the link.
LCAP—Link Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express device specific capabilities.
31:24
23:18
17:15
14:12
15:6
Bit
Bit
5
4
3
2
1
0
Access &
Default
Access &
R/WC
R/WC
R/WC
R/WC
Default
0 b
0 b
0 b
0 b
0 b
RO
R/WO
R/WO
010 b
010 b
02 h
RO
Reserved
Transactions Pending
0: All pending transactions (including completions for any outstanding non-posted
1: Indicates that the device has transaction(s) pending (including completions for
Reserved
Unsupported Request Detected
When set this bit indicates that the Device received an Unsupported Request. Errors
are logged in this register regardless of whether error reporting is enabled or not in
the Device Control Register.
Fatal Error Detected
When set this bit indicates that fatal error(s) were detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device Control
register.
Non-Fatal Error Detected
When set this bit indicates that non-fatal error(s) were detected. Errors are logged in
this register regardless of whether error reporting is enabled or not in the Device
Control register.
Correctable Error Detected
When set this bit indicates that correctable error(s) were detected. Errors are logged
in this register regardless of whether error reporting is enabled or not in the Device
Control register.
Port Number
Indicates the PCI Express port number for the given PCI Express link. Matches the
value in Element Self Description [31:24].
Reserved
L1 Exit Latency
Indicates the length of time this Port requires to complete the transition from L1
to L0. The value 010 b indicates the range of 2 µs to less than 4 µs. If this field is
required to be any value other than the default, BIOS must initialize it
accordingly.
Both bytes of this register that contain a portion of this field must be written
simultaneously in order to prevent an intermediate (and undesired) value from
ever existing.
L0s Exit Latency
Indicates the length of time this Port requires to complete the transition from L0s
to L0. The value 010 b indicates the range of 128 ns to less than 256 ns. If this
field is required to be any value other than the default, BIOS must initialize it
accordingly.
requests on any used virtual channel) have been completed.
any outstanding non-posted requests for all used Traffic Classes).
1
ACh
02012D01h
R/WO
16 bits
Description
Description
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