NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 115

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.45
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
RSTS—Root Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Provides information about PCI Express Root Complex specific parameters.
31:18
15:0
Bit
Bit
17
16
2
1
0
Access &
Access &
Default
Default
0000 h
R/W/C
R/W
R/W
R/W
0 b
0 b
0 b
0 b
0 b
RO
RO
System Error on Fatal Error Enable
Controls the Root Complex’s response to fatal errors.
0: No SERR generated on receipt of fatal error.
1: Indicates that an SERR should be generated if a fatal error is reported by any
System Error on Non-Fatal Uncorrectable Error Enable
Controls the Root Complex’s response to non-fatal errors.
0: No SERR generated on receipt of non-fatal error.
1: Indicates that an SERR should be generated if a non-fatal error is reported by
System Error on Correctable Error Enable
Controls the Root Complex’s response to correctable errors.
0: No SERR generated on receipt of correctable error.
1: Indicates that an SERR should be generated if a correctable error is reported
Reserved
PME Pending
Indicates that another PME is pending when the PME Status bit is set. When the
PME Status bit is cleared by software; the PME is delivered by hardware by setting
the PME Status bit again and updating the Requestor ID appropriately. The PME
pending bit is cleared by hardware if no more PMEs are pending.
PME Status
Indicates that the requestor ID indicated in the PME Requestor ID field asserted
PME. Subsequent PMEs are kept pending until the status register is cleared by
writing a 1 to this field.
PME Requestor ID
Indicates the PCI requestor ID of the last PME requestor.
of the devices in the hierarchy associated with this Root Port, or by the Root
Port itself.
any of the devices in the hierarchy associated with this Root Port, or by the
Root Port itself.
by any of the devices in the hierarchy associated with this Root Port, or by the
Root Port itself.
1
C0h
00000000h
RO, R/W/C
32 bits
Description
Description
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