NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 17

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Introduction
1.3
1.3.1
1.3.2
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
MCH Overview
The MCH connects to the processor as shown in
a system is to manage the flow of information between its four interfaces: the
processor interface (FSB), the system memory interface (DRAM controller), the DMI
interface, and the PCI Express port. This includes arbitrating between FSB, DMI and PCI
Express when each initiates an operation.
Host Interface
The MCH supports FSB speed of 533 MT/s (133 MHz), 800MT/s (200 MHz) and
1066 MT/s (266 MHz) using a scalable FSB Vcc_CPU. Other MCH supported features of
the host interface include: Hyper-Threading Technology (HT Technology), Pentium 4
and Pentium D processor FSB interrupt delivery, FSB Dynamic Bus Inversion (DBI),
12-deep In-Order Queue, and 1-deep Defer Queue.
The MCH supports 36-bit host addressing, decoding up to 8 GB of the processor’s
usable memory address space. Host initiated I/O cycles are decoded to PCI Express,
DMI, or the MCH configuration space. Host initiated memory cycles are decoded to PCI
Express, DMI or main memory. PCI Express device accesses to non-cacheable system
memory are not snooped on the host bus. Memory accesses initiated from PCI Express
using PCI semantics and from DMI to system SDRAM will be snooped on the host bus.
System Memory Interface
The MCH integrates a system memory DDR2 controller with two 64-bit wide interfaces.
Only Double Data Rate 2 (DDR2) memory is supported; consequently, the buffers
support only SSTL_1.8 V signal interfaces. The memory controller interface is fully
configurable through a set of control registers. Features of the MCH memory controller
include:
• Maximum memory size is 8 GB.
• The MCH System Memory Controller directly supports one or two channels of
• Supports DDR2 memory DIMM frequencies of 533 MHz and 667 MHz. The speed
• Available bandwidth up to 5.3 GB/s (DDR2 667) for single-channel mode or dual-
• Supports two channels of ECC DDR2 DIMMs (Each channel consists of 64 data lines
• Supports 256 Mb, 512 Mb and 1 Gb DDR2 technologies for x8 devices.
• Supports four banks for all DDR2 devices up to 512 Mb density. Supports eight
• DDR2-667 4-4-4 is not supported.
• Supports only unbuffered DIMMs.
memory (each channel consisting of 64 data lines).
used in all channels is the speed of the slowest DIMM in the system.
channel asymmetric mode, and 10.7 GB/s (DDR2 667) for dual-channel interleaved
mode.
plus eight additional bits for ECC).
banks for 1 Gb DDR2 devices.
— The memory channels are asymmetric: “Stacked” channels are assigned
— The memory channels are interleaved: Addresses are ping-ponged between the
addresses serially. Channel B addresses are assigned after all Channel A
addresses.
channels after each cache line (64 byte boundary).
Figure
1-1. A major role of the MCH in
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