NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 6

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

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Host-PCI Express Bridge Registers (D3:F0) (Intel® 3010 Chipset only) ............................ 129
6.1
Direct Media Interface (DMI) RCRB.............................................................................. 135
7.1
System Address Map ................................................................................................. 143
8.1
8.2
8.3
5.1.51 VC0RCAP—VC0 Resource Capability (D1:F0) ............................................ 118
5.1.52 VC0RCTL—VC0 Resource Control (D1:F0) ................................................ 118
5.1.53 VC0RSTS—VC0 Resource Status (D1:F0) ................................................. 119
5.1.54 VC1RCAP—VC1 Resource Capability (D1:F0) ............................................ 119
5.1.55 VC1RCTL—VC1 Resource Control (D1:F0) ................................................ 120
5.1.56 VC1RSTS—VC1 Resource Status (D1:F0) ................................................. 121
5.1.57 RCLDECH—Root Complex Link Declaration Enhanced
5.1.58 ESD—Element Self Description (D1:F0) ................................................... 122
5.1.59 LE1D—Link Entry 1 Description (D1:F0) ................................................... 122
5.1.60 LE1A—Link Entry 1 Address (D1:F0)........................................................ 123
5.1.61 LE2D—Link Entry 2 Description (D1:F0) ................................................... 123
5.1.62 LE2A—Link Entry 2 Address (D1:F0)........................................................ 124
5.1.63 UESTS—Uncorrectable Error Status (D1:F0) ............................................. 124
5.1.64 UEMSK—Uncorrectable Error Mask (D1:F0) .............................................. 125
5.1.65 CESTS—Correctable Error Status (D1:F0) ................................................ 126
5.1.66 CEMSK—Correctable Error Mask (D1:F0).................................................. 127
5.1.67 PEGSSTS—PCI Express link Sequence Status (D1:F0)................................ 128
Configuration Register Details (D3:F0)................................................................ 132
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
DMI RCRB Configuration Register Details ............................................................ 136
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10 DMIVC1RSTS—DMI VC1 Resource Status ................................................. 140
7.1.11 DMILCAP—DMI Link Capabilities ............................................................. 140
7.1.12 DMILCTL—DMI Link Control.................................................................... 141
7.1.13 DMILSTS—DMI Link Status .................................................................... 141
7.1.14 DMIUEMSK—DMI Uncorrectable Error Mask .............................................. 142
Legacy Address Range...................................................................................... 146
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
Main Memory Address Range (1 MB to TOLUD) .................................................... 149
8.2.1
8.2.2
8.2.3
PCI Memory Address Range (TOLUD to 4 GB) ...................................................... 151
8.3.1
Capability Header (D1:F0) ..................................................................... 121
DID3—Device Identification (D3:F0)........................................................ 132
LCAP3—Link Capabilities (D3:F0) ............................................................ 132
LSTS3—Link Status (D3:F0) ................................................................... 133
ESD3—Element Self Description (D3:F0).................................................. 134
LE2A3—Link Entry 2 Address (D3:F0) ...................................................... 134
DMIVCECH—DMI Virtual Channel Enhanced Capability Header .................... 136
DMIPVCCAP1—DMI Port VC Capability Register 1 ...................................... 136
DMIPVCCAP2—DMI Port VC Capability Register 2 ...................................... 137
DMIPVCCTL—DMI Port VC Control ........................................................... 137
DMIVC0RCAP—DMI VC0 Resource Capability ............................................ 137
DMIVC0RCTL0—DMI VC0 Resource Control .............................................. 138
DMIVC0RSTS—DMI VC0 Resource Status ................................................. 138
DMIVC1RCAP—DMI VC1 Resource Capability ............................................ 139
DMIVC1RCTL1—DMI VC1 Resource Control .............................................. 139
DOS Range (0h – 9_FFFFh).................................................................... 147
Legacy Area (A_0000h-B_FFFFh) ............................................................ 147
Expansion Area (C_0000h-D_FFFFh) ....................................................... 147
Extended System BIOS Area (E_0000h-E_FFFFh)...................................... 148
System BIOS Area (F_0000h-F_FFFFh) .................................................... 148
Programmable Attribute Map (PAM) Memory Area Details ........................... 149
ISA Hole (15 MB-16 MB)........................................................................ 150
TSEG .................................................................................................. 150
Pre-allocated Memory............................................................................ 150
APIC Configuration Space (FEC0_0000h-FECF_FFFFh)................................ 152
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet