NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 11

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Features
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Processor Interface
DMI Interface
PCI Express* Interface Support
— Supports a single Intel® Pentium® 4,
— Supports Pentium 4 processor FSB
— 533/800/1066 MT/s (133/200/266 MHz
— Supports Hyper-Threading Technology
— FSB Dynamic Bus Inversion (DBI)
— 36-bit host addressing for access to 8 GB of
— 12-deep In-Order Queue
— 1-deep Defer Queue
— GTL+ bus driver with integrated GTL
— Supports a Cache Line Size of 64 bytes
— A chip-to-chip connection interface to
— 2 GB/s point-to-point DMI to ICH7 (1 GB/s
— 100 MHz reference clock (shared with PCI
— 32-bit downstream addressing
— Messages and Error Handling
— Intel® 3000: one PCI Express port (x8/x4/
— Intel® 3010: two PCI Express ports (two
— Peer-to-peer Writes
Intel® Pentium® D, Intel® Celeron® D,
and Dual-Core Intel® Xeon® Processor
3000 Series in the LGA775 package
interrupt delivery
core) FSB
(HT Technology)
memory space
termination resistors
Intel® ICH7
each direction)
Express Interface)
x1)
x8/x4/x1, or one x16)
§
System Memory
Package
— Compatible with the PCI Express Base
— Raw bit rate on data pins of 2.5 Gb/s
— Maximum theoretical aggregate bandwidth
— 8 GB maximum memory
— Up to two 64-bit wide DDR2 SDRAM
— DDR2 memory DIMM frequencies of
— Asymmetric or Interleaved modes
— Bandwidth up to 10.7 GB/s (DDR2 667) in
— ECC (Error Correcting Code) memory
— 256 Mb, 512 Mb and 1 Gb DDR2
— Four banks for DDR2 devices up to 512 Mb
— Unbuffered DIMMs only
— Page sizes of 4 KB, 8 KB, and 16 KB
— Opportunistic refresh
— Up to 64 simultaneously open pages
— SPD (Serial Presence Detect) scheme for
— Supports configurations defined in the
— 34 mm x 34 mm, 1202 balls, non-grid
— Lead Free MCH
Specification Revision 1.0a
resulting in a real bandwidth per pair of
250 MB/s
of 8 GB/s when x16
channels
533 MHz and 667 MHz.
dual- channel Interleaved mode
technologies
density; eight banks for 1 Gb DDR2 devices
DIMM detection support
JEDEC DDR2 DIMM specification only
pattern
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