NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 122

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.58
5.1.59
122
ESD—Element Self Description (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Provides information about the root complex element containing this Link Declaration
Capability.
LE1D—Link Entry 1 Description (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
First part of a Link Entry, which declares an internal link to another Root Complex
Element.
31:24
23:16
31:24
23:16
15:8
7:4
3:0
Bit
Bit
Access & Default
01 h (Intel® 3000
02 h (Intel® 3010
Access &
Default
R/WO
00 h
00 h
RO
chipset)
chipset)
R/WO
02 h
00 h
0 h
RO
RO
RO
Target Port Number
Specifies the port number associated with the element targeted by this link entry
(Egress Port). The target port number is with respect to the component that contains
this element as specified by the target component ID.
Target Component ID
Identifies the physical or logical component that is targeted by this link entry. A
value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
1
144h
02000100h02000200h
RO, R/WO
32 bits
1
150h
00000000h
RO, R/WO
32 bits
Port Number
Specifies the port number associated with this element with respect to the
component that contains this element. The egress port of the component to
provide arbitration to this Root Complex Element utilizes this port number
value.
Component ID
Identifies the physical component that contains this Root Complex Element.
Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in
this component. The value only needs to be written in one of the mirrored
fields and it will be reflected everywhere that it is mirrored.
Number of Link Entries
Indicates the number of link entries following the Element Self Description.
This field reports 01h on Intel® 3000 chipset, and 02h on Intel® 3010
chipset (to Egress port and to the other PCI Express port).
Reserved
Element Type
Indicates the type of the Root Complex Element.
Value of 0 h represents a root port.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Host-PCI Express Bridge Registers (D1:F0)
Description