NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 69

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.1.36
4.1.37
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
SMICMD - SMI Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
SCICMD - SCI Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
15:2
15:2
Bit
Bit
1
0
1
0
Access &
Access &
Default
Default
R/W
R/W
R/W
R/W
0 b
0 b
0b
0b
Reserved
SMI on Multiple-Bit DRAM ECC Error (DMESMI):
SMI on Single-bit ECC Error (DSESMI):
Reserved
SCI on Multiple-Bit DRAM ECC Error (DMESCI):
SCI on Single-bit ECC Error (DSESCI):
0
CC-CDh
0000h
RO; R/W;
16 bits
0
CE-CFh
0000h
RO; R/W;
16 bits
1: The MCH generates an SMI DMI message when it detects a multiple-bit
0: Reporting of this condition via SMI messaging is disabled. For systems not
1: The MCH generates an SMI DMI special cycle when the DRAM controller
0: Reporting of this condition via SMI messaging is disabled. For systems that
1: The MCH generates an SCI DMI message when it detects a multiple-bit
0: Reporting of this condition via SCI messaging is disabled. For systems not
1: The MCH generates an SCI DMI special cycle when the DRAM controller
0: Reporting of this condition via SCI messaging is disabled. For systems that
error reported by the DRAM controller.
supporting ECC this bit must be disabled.
detects a single bit error.
do not support ECC this bit must be disabled.
error reported by the DRAM controller.
supporting ECC this bit must be disabled.
detects a single bit error.
do not support ECC this bit must be disabled.
Description
Description
69