NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 90

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1
5.1.1
5.1.2
5.1.3
90
Configuration Register Details (D1:F0)
VID1—Vendor Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register combined with the Device Identification register uniquely identifies any
PCI device.
DID1—Device Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
PCICMD1—PCI Command (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
15:0
15:0
Bit
15:11
Bit
Bit
10
9
Access &
Default
Access &
2779h
Default
8086 h
RO
Access &
Default
RO
R/W
0 b
RO
0 b
Device Identification Number (DID1)
Identifier assigned to the MCH device 1 (virtual PCI-to-PCI bridge, PCI Express port).
Vendor Identification (VID1)
PCI standard identification for Intel.
Reserved
INTA Assertion Disable
0: This device is permitted to generate INTA interrupt messages.
1: This device is prevented from generating interrupt messages.
Any INTA emulation interrupts already asserted must be de-asserted when this bit
is set.
Only affects interrupts generated by the device (PCI INTA from a PME or Hot Plug
event) controlled by this command register. It does not affect upstream MSIs,
upstream PCI INTA-INTD asserts and de-assert messages.
Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. Hardwired to 0.
1
00h
8086h
RO
16 bits
1
02h
2779h
RO
16 bits
1
04h
0000h
RO, R/W
16 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Host-PCI Express Bridge Registers (D1:F0)