NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 8

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

12
Figures
8
Testability................................................................................................................ 205
12.1
12.2
12.3
12.4
12.5
1-1
1-2
2-1
3-1
3-2
3-3
3-4
4-1
8-1
8-2
8-3
8-4
9-1
9-2
9-3
9-4
9-5
11-1 MCH Ballout Diagram (Top View – Left Side) ....................................................... 180
11-2 MCH Ballout Diagram (Top View – Right Side) ..................................................... 181
11-3 MCH Package Dimensions (Top View) ................................................................. 202
11-4 MCH Package Dimensions (Side View) ................................................................ 202
11-5 MCH Package Dimensions (Bottom View) ............................................................ 203
12-1 XOR Test Mode Initialization Cycles .................................................................... 206
Complimentary Pins ......................................................................................... 205
XOR Test Mode Initialization.............................................................................. 205
XOR Chain Definition ........................................................................................ 206
XOR Chains..................................................................................................... 207
Pads Excluded from XOR Mode(s) ...................................................................... 218
Intel® 3000 Chipset System Block Diagram Example .............................................14
Intel® 3010 Chipset System Block Diagram Example .............................................15
Signal Information Diagram ................................................................................22
Conceptual Platform PCI Configuration Diagram .....................................................35
Register Organization .........................................................................................36
Memory Map to PCI Express Device Configuration Space .........................................38
MCH Configuration Cycle Flow chart .....................................................................40
Link Declaration Topology ...................................................................................82
System Address Ranges ................................................................................... 145
Microsoft MS-DOS* Legacy Address Range .......................................................... 146
Main Memory Address Range............................................................................. 149
PCI Memory Address Range .............................................................................. 152
System Memory Styles ..................................................................................... 161
PCI Express Related Register Structures in MCH................................................... 166
Lane Reversal (Dual PCI Express Configuration Example) ...................................... 168
Dual PCI Express Microarchitecture .................................................................... 170
PCI Express Error Handling Flow ........................................................................ 171
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet