NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 19

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Introduction
1.3.5
1.3.6
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
System Interrupts
MCH Clocking
The differential Host clock (HCLKP/HCLKN) is set to 133/200/266 MHz, supporting
transfer rates of 533/800/1066 MT/s, respectively. The Host PLL generates 2x, 4x, and
8x versions of the host clock for internal optimizations. The MCH core clock is
synchronized to the host clock.
The internal and external Memory clocks of 266 and 333 MHz are generated from one
of two MCH PLLs that use the Host clock as a reference. Also included are 2x and 4x
clocks for internal optimizations.
The PCI Express core clock of 250 MHz is generated from separate PCI Express PLL.
This clock uses the fixed 100 MHz Serial Reference Clock (GCLKP/GCLKN) for reference.
All of the above mentioned clocks are capable of tolerating Spread Spectrum clocking
as defined in the Clock Generator Specification. Host, Memory, and PCI Express PLLs,
and all associated internal clocks are disabled until PWROK is asserted.
• Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of
• Maximum theoretical realized bandwidth on interface of 4 GB/s in each direction
• PCI Express Extended Configuration Space. The first 256 bytes of configuration
• PCI Express Enhanced Addressing Mechanism accesses the device configuration
• Automatic discovery, negotiation, and training of link out of reset
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
• Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e.,
• Peer-to-peer Writes
• Supports both 8259 and Pentium 4 processor FSB interrupt delivery mechanisms
• Supports interrupts signaled as upstream Memory Writes from PCI Express and
250 MB/s given the 8b/10b encoding used to transmit data across this interface
simultaneously, for an aggregate of 8 GB/s when x16
space alias directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4 KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
space in a flat memory mapped fashion
normal PCI 2.3 Configuration space as a PCI-to-PCI Bridge)
DMI
— MSIs routed directly to FSB
— From I/OxAPICs
— Provides redirection for IPI (Inter-Processor Interrupts) and upstream
interrupts to the FSB
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