NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 3

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Contents
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Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Introduction............................................................................................................... 13
1.1
1.2
1.3
Signal Description....................................................................................................... 21
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
MCH Register Description ............................................................................................ 33
3.1
3.2
3.3
3.4
3.5
Host Bridge Registers (Device 0, Function 0) .................................................................. 45
4.1
Terminology ..................................................................................................... 15
Reference Documents ........................................................................................ 16
MCH Overview .................................................................................................. 17
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
Host Interface Signals ........................................................................................ 23
DDR2 DRAM Channel A Interface ......................................................................... 25
DDR2 DRAM Channel B Interface ......................................................................... 26
DDR2 DRAM Reference and Compensation ............................................................ 27
PCI Express* Interface Signals ............................................................................ 27
Clocks, Reset, and Miscellaneous ......................................................................... 28
Direct Media Interface (DMI)............................................................................... 28
Power, Ground .................................................................................................. 29
Reset States and Pull-up/Pull-downs .................................................................... 29
Register Terminology ......................................................................................... 34
Platform Configuration ....................................................................................... 35
Configuration Mechanism ................................................................................... 37
3.3.1
3.3.2
Routing Configuration Accesses ........................................................................... 39
3.4.1
3.4.2
I/O Mapped Registers ........................................................................................ 42
3.5.1
3.5.2
Configuration Register Details (D0:F0) ................................................................. 47
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10 SID—Subsystem Identification (D0:F0) ..................................................... 51
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ....................................................... 52
4.1.12 EPBAR—Egress Port Base Address (D0:F0) ................................................ 52
4.1.13 MCHBAR—MCH Memory Mapped Register Range Base Address (D0:F0) ......... 53
Host Interface........................................................................................ 17
System Memory Interface ....................................................................... 17
Direct Media Interface (DMI).................................................................... 18
PCI Express* Interface(s)........................................................................ 18
System Interrupts .................................................................................. 19
MCH Clocking ........................................................................................ 19
Power Management ................................................................................ 20
Standard PCI Configuration Mechanism ..................................................... 37
PCI Express Enhanced Configuration Mechanism......................................... 38
Internal Device Configuration Accesses ..................................................... 41
Bridge Related Configuration Accesses ...................................................... 41
CONFIG_ADDRESS—Configuration Address Register ................................... 43
CONFIG_DATA—Configuration Data Register .............................................. 44
VID—Vendor Identification (D0:F0)........................................................... 47
DID—Device Identification (D0:F0) ........................................................... 47
PCICMD—PCI Command (D0:F0) .............................................................. 48
PCISTS—PCI Status (D0:F0) .................................................................... 49
RID—Revision Identification (D0:F0) ......................................................... 50
CC—Class Code (D0:F0) .......................................................................... 50
MLT—Master Latency Timer (D0:F0) ......................................................... 50
HDR—Header Type (D0:F0) ..................................................................... 51
SVID—Subsystem Vendor Identification (D0:F0)......................................... 51
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