NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 144

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

144
Device 1, Function 0:
Device 3, Function 0:
The rules for the above programmable ranges are:
Figure 8-1
• ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
• In the case of overlapping ranges with memory, the memory decode will be given
• There are NO Hardware Interlocks to prevent problems in the case of overlapping
• Accesses to overlapped ranges may produce indeterminate results.
• The only peer-to-peer cycles allowed below the top of memory (register TOLUD)
system designer’s responsibility to limit memory population so that adequate PCI,
PCI Express, High BIOS, PCI Express Memory Mapped space, and APIC memory
space can be allocated.
priority.
ranges.
are DMI to PCI Express VGA range writes.
A. MBASE1/MLIMIT1 – Primary PCI Express port non-prefetchable memory access
B. PMBASE1/PMLIMIT1 – Primary PCI Express port prefetchable memory access
C. IOBASE1/IOLIMIT1 – Primary PCI Express port I/O access window.
A. MBASE3/MLIMIT3 – Secondary PCI Express port non-prefetchable memory
B. PMBASE3/PMLIMIT3 – Secondary PCI Express port prefetchable memory
C. IOBASE3/IOLIMIT3 – Secondary PCI Express port I/O access window.
window.
window.
access window.
access window.
represents system memory address map in a simplified form.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
System Address Map