NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 15

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Introduction
Figure 1-2.
1.1
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Intel® 3010 Chipset System Block Diagram Example
Terminology
Core
DED
DBI
DDR2
DMI
ECC
FSB
Full Reset
Host
Term
AC '97/Intel® HD Audio
The internal base logic in the MCH
Double-bit Error Detect
Dynamic Bus Inversion
A second generation Double Data Rate SDRAM memory technology
MCH-ICH Direct Media Interface is the chip-to-chip connection between the MCH and
ICH7. This interface is based on the standard PCI Express specification.
Error Correcting Code
Front Side Bus. This term is synonymous with Host bus or processor bus.
Full reset is when PWROK is deasserted. Warm reset is when both RSTIN# and PWROK
are asserted.
This term is used synonymously with processor.
USB 2.0 (8)
PCI Express*
2 x8/x4/x1
SATA (4)
PCI Bus
ATA100
1 x16
or
Intel® 3010 MCH
Firmware Hub
Intel
Processor
®
ICH7
LPC 1/F
DMI
FSB 533/800/1066 MT/s
Description
SPI
x1
x1
Intel® Pro/1000
Intel® Pro/1000
Super I/O
PM/PL LAN
PM/PL LAN
Connection
Connection
DDR2 533/667
DDR2 533/667
PCI Express
1 x4 or 4 x1
SPI
GbE
GbE
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