NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 76

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.2.8
4.2.9
76
C0BNKARC—Channel A DRAM Bank Architecture
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
This register is used to program the bank architecture for each Rank.
C0DRT1—Channel A DRAM Timing Register
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
31:23
22:19
18:10
15:8
7:6
5:4
3:2
1:0
9:8
Bit
Bit
7
Access &
Access &
Default
Default
00 b
00 b
00 b
00 b
R/W
R/W
R/W
R/W
01 b
R/W
R/W
9 h
Reserved
Rank 3 Bank Architecture
Rank 2 Bank Architecture
Rank 1 Bank Architecture
Rank 0 Bank Architecture
Reserved
Activate to Precharge delay (tRAS). This bit controls the number of DRAM
clocks for tRAS. Minimum recommendations are beside their corresponding
encodings.
Reserved
CASB Latency (tCL). This field is programmable on DDR2 DIMMs. The value
programmed here must match the CAS Latency of every DDR2 DIMM in the
system.
Reserved
00:4 Bank.
01:8 Bank.
1X:Reserved
00:4 Bank.
01:8 Bank.
1X:Reserved
00:4 Bank.
01:8 Bank.
1X:Reserved
00:4 Bank.
01:8 Bank.
1X:Reserved
MCHBAR
0
10E-10Fh
0000h
R/W
16 bits
MCHBAR
114-117h
02483D22h
R/W
32 bits
0h – 3hReserved
4h – FhFour to Fifteen Clocks respectively.
Encoding DDR2 CL
00: 5
01: 4
10: 3
11: Reserved
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description
Description