NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 157

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

System Address Map
8.5.4
Table 8-6.
8.5.5
8.5.6
8.5.7
8.5.8
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS software
can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range
access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be
forwarded to the DMI or PCI Express. The SMM software can use this bit to write to
memory while running SMM code out of DRAM.
SMM Control Table
SMM Space Decode and Transaction Handling
Only the CPU is allowed to access SMM space. PCI Express and DMI originated
transactions are not allowed to SMM space.
CPU WB Transaction to an Enabled SMM Address Space
CPU Writeback transactions (HREQ[1]# = 0) to enabled SMM Address Space must be
written to the associated SMM DRAM even though D_OPEN=0 and the transaction is
not performed in SMM mode. This ensures SMM space cache coherency when cacheable
extended SMM space is used.
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
“shadowed” into MCH DRAM memory. Typically this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. CPU bus transactions are
routed accordingly.
I/O Address Space
The MCH does not support the existence of any other I/O devices beside itself on the
CPU bus. The MCH generates either DMI or PCI Express bus cycles for all CPU I/O
accesses that it does not claim. Within the host bridge the MCH contains two internal
registers in the CPU I/O space, Configuration Address Register (CONFIG_ADDRESS)
and the Configuration Data Register (CONFIG_DATA). These locations are used to
implement a configuration space access mechanism.
G_SMRAME
0
1
1
1
1
1
1
1
1
D_LCK
0
0
0
0
0
1
1
1
x
D_CLS
X
X
0
0
1
1
X
0
1
D_OPEN
0
0
1
0
1
x
x
x
x
CPU in SMM
Mode
x
0
1
x
1
x
0
1
1
SMM Code
Access
Disable
Disable
Disable
Enable
Enable
Enable
Invalid
Enable
Enable
SMM Data
Access
Disable
Disable
Disable
Disable
Disable
Invalid
Enable
Enable
Enable
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