NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet
NH82801GR S L8FY
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NH82801GR S L8FY Summary of contents
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... Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet November 2008 Reference Number: 313953 Revision: 002 ...
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... Intel® 3000 and 3010 chipsets may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... SVID—Subsystem Vendor Identification (D0:F0)......................................... 51 4.1.10 SID—Subsystem Identification (D0:F0) ..................................................... 51 4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ....................................................... 52 4.1.12 EPBAR—Egress Port Base Address (D0:F0) ................................................ 52 4.1.13 MCHBAR—MCH Memory Mapped Register Range Base Address (D0:F0) ......... 53 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 3 ...
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... PMCFG—Power Management Configuration.................................................81 4.2.24 PMSTS—Power Management Status...........................................................81 4.3 Egress Port Register Summary ............................................................................82 4.3.1 EPESD—EP Element Self Description..........................................................83 4.3.2 EPLE1D—EP Link Entry 1 Description .........................................................83 4.3.3 EPLE1A—EP Link Entry 1 Address..............................................................84 4 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... PCI_EXPRESS_LC—PCI Express link Legacy Control .................................. 116 5.1.47 VCECH—Virtual Channel Enhanced Capability Header (D1:F0) .................... 116 5.1.48 PVCCAP1—Port VC Capability Register 1 (D1:F0) ...................................... 117 5.1.49 PVCCAP2—Port VC Capability Register 2 (D1:F0) ...................................... 117 5.1.50 PVCCTL—Port VC Control (D1:F0) ........................................................... 118 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 5 ...
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... CESTS—Correctable Error Status (D1:F0) ................................................ 126 5.1.66 CEMSK—Correctable Error Mask (D1:F0).................................................. 127 5.1.67 PEGSSTS—PCI Express link Sequence Status (D1:F0)................................ 128 6 Host-PCI Express Bridge Registers (D3:F0) (Intel® 3010 Chipset only) ............................ 129 6.1 Configuration Register Details (D3:F0)................................................................ 132 6.1.1 DID3— ...
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... Absolute Minimum and Maximum Ratings ........................................................... 173 10.2 Power Characteristics....................................................................................... 174 10.3 Signal Groups ................................................................................................. 175 10.4 DC Characteristics ........................................................................................... 177 11 Ballout and Package Information ................................................................................ 179 11.1 Ballout ........................................................................................................... 179 11.2 MCH Ballout Table ........................................................................................... 182 11.3 Package ......................................................................................................... 202 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 7 ...
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... MCH Ballout Diagram (Top View – Right Side) ..................................................... 181 11-3 MCH Package Dimensions (Top View) ................................................................. 202 11-4 MCH Package Dimensions (Side View) ................................................................ 202 11-5 MCH Package Dimensions (Bottom View) ............................................................ 203 12-1 XOR Test Mode Initialization Cycles .................................................................... 206 8 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... XOR Chain #4................................................................................................. 212 12-8 XOR Chain #5................................................................................................. 213 12-9 XOR Chain #6................................................................................................. 214 12-10 XOR Chain #7................................................................................................. 215 12-11 XOR Chain #8................................................................................................. 216 12-12 XOR Chain #9................................................................................................. 218 12-13 XOR Pad Exclusion List ..................................................................................... 218 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 9 ...
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... Revision History Rev Description • Changed VTT Min to 0.9975 in 002 Characteristics” on page 177. 001 • Initial Release 10 Date Table 10-5, “DC November 2008 August 2006 § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Intel® 3010: two PCI Express ports (two x8/x4/x1, or one x16) — Peer-to-peer Writes Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet — Compatible with the PCI Express Base Specification Revision 1.0a — Raw bit rate on data pins of 2.5 Gb/s ...
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... Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Intel® 3000 and Intel® 3010 chipsets, respectively. Intel® 3000 chipset supports one x8 PCI Express port and supports two x8 PCI Express ports or one x16 PCI Express port. Neither Intel® 3000 chipset nor Intel® 3010 chipset supports PCI Express graphics ...
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... DMI USB 2.0 (8) SATA (4) ATA100 ® Intel ICH7 PCI Bus SPI LPC 1/F Firmware Hub Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Introduction DDR2 533/667 DDR2 533/667 Intel® Pro/1000 x1 GbE PM/PL LAN Connection Intel® Pro/1000 x1 ...
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... Full reset is when PWROK is deasserted. Warm reset is when both RSTIN# and PWROK Full Reset are asserted. This term is used synonymously with processor. Host Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Processor FSB 533/800/1066 MT/s PCI Express* 2 x8/x4/x1 Intel® ...
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... PCI Express port. It communicates with the I/O controller hub (Intel® MCH ICH7) over the DMI. Throughout this document, MCH refers to the Intel® 3000 MCH and Intel® 3010 MCH, unless otherwise specified. Message Signaled Interrupt. A transaction initiated outside the host, conveying interrupt ...
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... Supports four banks for all DDR2 devices up to 512 Mb density. Supports eight banks for 1 Gb DDR2 devices. • DDR2-667 4-4-4 is not supported. • Supports only unbuffered DIMMs. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Figure 1-1. A major role of the MCH in 17 ...
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... PCI Express port fully compatible to the PCI Express Base Specification, Revision 1.0a. • Intel® 3000 chipset supports one x8 PCI Express port • Intel® 3010 chipset supports two x8 PCI Express ports, or one x16 PCI Express port. • Base PCI Express frequency of 2.5 Gb/s only 18 Intel® ...
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... All of the above mentioned clocks are capable of tolerating Spread Spectrum clocking as defined in the Clock Generator Specification. Host, Memory, and PCI Express PLLs, and all associated internal clocks are disabled until PWROK is asserted. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 19 ...
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... ACPI Rev 1.0 compatible power management • Supports processor states: C0 and C1 • Supports system states: S0, S4 and S5 • Supports processor Thermal Management 2 (TM2) • Microsoft Windows* NT Hardware Design Guide v1.0 compliant 20 § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Introduction ...
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... High Voltage CMOS input-only buffers. 3.3 V tolerant. SSTL-1.8 Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V tolerant. A Analog reference or output. These signals may be used as a threshold voltage or for buffer compensation. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 21 ...
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... SBS_B[2:0] System SRAS_B# Memory SCAS_B# SWE_B# DDR2 Channel SDM_B[7:0] B SCB_B[7:0] Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Description EXP_RX0N[7:0], EXP_RX0P[7:0] EXP_RX1N[7:0]†, EXP_RX1P[7:0]† EXP_TX0N[7:0], EXP_TX0P[7:0] EXP_TX1N[7:0]†, EXP_TX1P[7:0]† EXP_COMPO EXP_COMPI PRIPRSNT#† DPEN#† ...
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... GTL+ HA[35:3]# GTL+ HADSTB[1:0]# GTL+ Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ). TT I/O Address Strobe: The CPU bus owner asserts HADS# to indicate the first of two cycles of a request phase. The MCH can assert this signal for snoop cycles and interrupt messages ...
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... I Bus Speed Select: At the de-assertion of RSTIN#, the value sampled on these pins determines the expected frequency of the bus. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Description Description Data Bits HD[63:48]# HDINV[3]# HD[47:32]# ...
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... SRAS_A# SCAS_A# SWE_A# SDQ_A[63:0] SDM_A[7:0] SDQS_A[8:0] Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet I Slew Rate Compensation Select: 1: Normal Operation - use Lookup table for slew compensation value. 0: Use SCOMP circuit for slew compensation value. I/O Host RCOMP: This signal is used to calibrate the Host GTL+ I/O buffers. ...
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... Clock Enable: (1 per Rank) SCKE_B is used to initialize the SSTL-1.8 SDRAMs during power-up, and to power-down SDRAM ranks Die Termination: These signals are Active On-die Termination SSTL-1.8 control signals for DDR2 devices. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Description Description Description ...
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... EXP_TX1P[7:0] † EXP_COMPO EXP_COMPI EXP_SLR PRIPRSNT# † DPEN# † Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Type I/O System Memory RCOMP I/O DDR2 On-Die DRAM Over Current Detection (OCD) driver A compensation I SDRAM Reference Voltage: Reference voltage inputs for DQ, CB, A DQS, and DQS# input signals ...
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... All Z Test: This signal is used for Bed of Nails testing by OEMs to GTL+ execute ALL Z test. Type I Direct Media Interface: Receive differential pair (Rx) DMI O Direct Media Interface: Transmit differential pair (Tx) DMI Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Description Description Description ...
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... CMCT: Common Mode Center Tapped. Differential signals are weakly driven to the common mode central voltage. STRAP: Strap input sampled on the asserting edge of PWROK. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Voltage 1.5 V Core Power 1.2 V Processor System Bus Termination Power 1 ...
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... TERM HV O TERM HV TERM HV O TERM HV TERM HV O TERM HV TERM HV I TERM HV TERM I/O TRI TRI after RCOMP I/O TRI TRI TERM HV STRAP HV Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Description Pull-up/ Pull-down RCOMP Short to ground ...
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... SWE_B# SDQ_B[63:0] SCB_B[7:0] SDM_B[7:0] SDQS_B[8:0] SDQS_B[8:0]# SCKE_B[3:0] SODT_B[3:0] SYSTEM SRCOMP0 MEMORY SRCOMP1 (Misc.) SVREF[1:0] SOCOMP[1:0] Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet State After State During I/O RSTIN# RSTIN# Assertion Deassertion O TRI TRI O TRI TRI O TRI TRI ...
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... I/O TRI STRAP I/O TERM HV STRAP I/O TERM HV STRAP § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Description State After Pull-up/ RSTIN# Pull-down Deassertion CMCT CMCT CMCT 1.0V CMCT 1.0V TRI TRI TERM HV TRI Internal PU TRI ...
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... When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be 8-, 16-, or 32-bits in size). Writes to “Reserved” registers have no effect on the MCH. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads from “ ...
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... Write Only. Whose bits may be written, but will always-return zeros when read. They are used for write side effects. Any data written to these registers cannot be retrieved. 34 Description Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet MCH Register Description ...
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... Express base address register, DRAM control (including thermal/throttling control), and configuration for the DMI and other MCH specific registers. • Device 1 and Device 3 (Device 3 is for Intel® 3010 chipset only): Host-PCI Express Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compatible with PCI Express Specification Rev 1 ...
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... Note: Throughout this document, Device 3 is for Intel® 3010 chipset only. Figure 3-2. Register Organization 000h Device Config Registers PCI Express* FFFh PCI Express* Controls: Analog Controls Error Reporting Controls VC Controls Hot Plug/Slot Controls 0FFh Device Level Controls 000h Device 0 Config ...
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... The MCH is responsible for translating and routing the CPU’s I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration registers, DMI or PCI Express. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Device# Device 0 Device 1 and 3 ...
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... Device 31 Function 7 0xFFFF 0x1FFF Device 1 Function 1 0x7FFF 0xFFF Device 0 Function 0 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet MCH Register Description 0xFFF PCI Express Extended Configuration Space 0xFF PCI Compatible Configuration Space 0x3F PCI Compatible Configuration ...
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... ICH7 via DMI. Configuration cycles to both the PCI compatibility configuration space and the PCI Express extended configuration space are routed to the PCI Express port device or associated link. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 39 ...
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... No MCH Generates DMI MCH Generates DMI Type 0 Configuration Type 1Configuration Cycle Yes MCH Generates Type 0 Access to PCI Express Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet MCH Register Description Yes MCH Claims Func Yes MCH Claims = 0 No Cycle ...
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... Internally, the host interface unit translates writes to PCI Express extended configuration space to configuration writes on the backbone. • Writes to extended space are posted on the FSB, but non-posted on the PCI Express or DMI (i.e. translated to configuration writes) Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 41 ...
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... Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window. 42 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet MCH Register Description ...
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... R/W 00h 10:8 R/W 000b 7:2 R/W 00h 1:0 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0CF8h-0CFBh Accessed 00000000h R/W 32 bits Description Configuration Enable (CFGE Enable. Accesses to PCI configuration space are enabled Disable. Reserved Bus Number If the Bus Number is programmed to 00h the target of the Configuration Cycle is a PCI Bus #0 agent ...
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... If bit 31 of CONFIG_ADDRESS is 1, any I/O access to the CONFIG_DATA register will produce a configuration transaction using the contents of CONFIG_ADDRESS to determine the bus, device, function, and offset of the register to be accessed. § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet MCH Register Description ...
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... PCI 2.3 specification, but are not necessary or implemented in this component are not included in this document. Warning: Address locations that are not listed are considered Intel Reserved registers locations. Reads to Reserved address locations may return non-zero values. Writes to reserved locations may cause system failures. ...
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... SMI Command SCICMD SCI Command — Reserved SKPD Scratchpad Data CAPID0 Capability Identifier EDEAP Extended DRAM Error Address Pointer Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Default Value Access 00h RO/S 00h RO/S — — 00h R/W 00h ...
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... Size: This register, combined with the Vendor Identification register, uniquely identifies any PCI device. Bit Access & Default 15:0 RO 2778h Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 00-01h 8086h RO 16 bits Description Vendor Identification Number (VID): PCI standard identification for Intel. ...
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... Note: This bit only controls SERR messaging for the Device 0. Device 1 (and Device 3 for Intel® 3010 chipset) has its own SERRE bits to control error reporting for error conditions occurring in that device. The control bits are used in a logical OR manner to enable the SERR DMI message mechanism. ...
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... 3:0 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 06-07h 0090h RO, R/WC 16 bits Description Detected Parity Error (DPE): Not implemented. Hardwired to 0. Signaled System Error (SSE): Software clears this bit by writing it. 0: MCH Device 0 did Not generate a SERR message over DMI 1: MCH Device 0 generated a SERR message over DMI for any enabled Device 0 error condition ...
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... This is an 8-bit value that indicates the programming interface of this device. This value does not specify a particular register set layout and provides no practical use for this device. 0 0Dh 00h RO 8 bits Description Reserved Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Size: This register is used to identify a particular subsystem. Access & Bit Default 15:0 R/WO 0000 h Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 0Eh 00h RO 8 bits Description PCI Header (HDR): This field always returns 0 to indicate that the MCH is a single function device with standard header layout ...
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... System software uses this base address to program the MCH MMIO register set. Reserved EPBAR enable (EPBAREN): 0: EPBAR is disabled and does not claim any memory 1: EPBAR memory mapped accesses are claimed and decoded appropriately Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... This base address shall be assigned on a boundary consistent with the number of buses (defined by the Length field in this register), above TOLUD and still within total 36 bit addressable memory space. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 44-47h ...
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... PCIEXBAR register. PCIEXBAR bits 31:26 are R/W with no functionality behind them. 1: The PCIEXBAR register is enabled. Memory read and write transactions whose address bits 31:26 match PCIEXBAR will be translated to configuration reads and writes within the MCH. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Access & Bit Default 31:12 R/W 00000 h 11:1 0 R/W 0b Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 4C-4Fh 00000000h R/W 32 bits Description DMI Base Address: This field corresponds to bits the base address DMI configuration space. BIOS will program this register resulting in a base address for block of contiguous memory address space ...
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... Once the error flag bits are set as a result of an error, this bit field is locked and doesn't change as a result of a new error. These bits are reset on PWROK. Reserved Channel Indicator (CHI): This bit indicates which memory channel had the error. 0: Channel 0 1: Channel 1 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... DEAP. Access & Bit Default 7:6 5:0 RO/S 00 0000b Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 5Ch 00h RO/S; 8 bits Description DRAM ECC Syndrome (DECCSYN): After a DRAM ECC error on any QWord of the data chunk resulting from a read command, hardware loads this field with a syndrome that describes the set of bits associated with the first QWord containing an error ...
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... Only: All reads are sent to DRAM. All writes are forwarded to the DMI. 10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11:Normal DRAM Operation: All reads and writes are serviced by DRAM. Reserved Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Default 7:6 5:4 R 3:2 1:0 R Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 91h 00h R/W 8 bits Description Reserved 0C4000-0C7FFF Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0C4000 to 0C7FFF. ...
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... Only: All reads are serviced by DRAM. All writes are forwarded to the DMI. 10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI. 11:Normal DRAM Operation: All reads and writes are serviced by DRAM. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Default 7:6 5:4 R 3:2 1:0 R Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 95h 00h R/W 8 bits Description Reserved 0E4000-0E7FFF Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0E4000 to 0E7FFF. ...
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... VGA and MDA memory cycles can only be routed across the PCI Express lanes when MAE (PCICMD1[1]) is set. VGA and MDA I/O cycles can only be routed across the PCI Express lanes if IOAE (PCICMD1[0]) is set. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description ...
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... Access: Size: Access & Bit Default 15:10 9:0 R/W 00h Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 98-99h 03FFh R/W; 16 bits Description Reserved Remap Base Address [35:26] (REMAPBASE): The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address ...
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... SMM space to update the display even when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Note that the D_CLS bit only applies to Compatible SMM space. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset ...
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... NOT necessarily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory mapped I/O). These bits correspond to address bits 35:27 (128 MB granularity). Bits 26:0 are assumed Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... R/WC 7:2 1 R/WC R/WC Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 C8-C9h 0000h R/WC/ bits Description Reserved MCH Thermal Sensor Event for SMI/SCI/SERR: This bit indicates that a MCH Thermal Sensor trip has occurred and an SMI, SCI or SERR has been generated. The status bit is set only if a message is sent based on Thermal event enables in Error command, SMI command and SCI command registers ...
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... The MCH generates an SERR special cycle over DMI when the DRAM controller detects a single bit error. 0: Reporting of this condition via SERR messaging is disabled. For systems that do not support ECC this bit must be disabled. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Access & Bit Default 15 R/W 0b Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0 CC-CDh 0000h RO; R/W; 16 bits Description Reserved SMI on Multiple-Bit DRAM ECC Error (DMESMI): 1: The MCH generates an SMI DMI message when it detects a multiple-bit error reported by the DRAM controller. ...
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... Extended Error Address Pointer (EEAP): This bit provides bit 32 of the error address after any remapping when an ECC error occurs. This bit is concatenated with bits 31:7 of the DEAP register to get bits 32:7 of the address in which an error occurred. This bit is reset on PWROK. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... C1DRC1 F10–F13h PMCFG F14–F17h PMSTS Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Register Name Channel 0 DRAM Rank Boundary Address 0 Channel 0 DRAM Rank Boundary Address 1 Channel 0 DRAM Rank Boundary Address 2 Channel 0 DRAM Rank Boundary Address 3 ...
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... C0DRB3 = C1DRB3 = Total memory in chA rank0 + chA rank1+ chA rank2 + chA rank3 ( increments) 72 Host Bridge Registers (Device 0, Function 0) MCHBAR 100h 00h R/W 8 bits 100h 101h 102h 103h 180h 181h 182h 183h Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Access: Size: The operation of this register is detailed in the description for register C0DRB0. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description Channel A DRAM Rank Boundary Address: This 8 bit value defines the upper and lower addresses for each DRAM rank. Bits 6:2 are compared against Address 31:27 to determine the upper address limit of a particular rank. Bits 1:0 must be 0s. Bit 7 may be programmed to a ‘ ...
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... KB 011:8 KB 100:16 KB Others:Reserved Reserved Channel A DRAM even Rank Attribute: This 3 bit field defines the page size of the corresponding rank. 000:Unpopulated 001:Reserved 010:4 KB 011:8 KB 100 Others:Reserved MCHBAR 109h 8 bits Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... Since there are multiple clock signals assigned to each Rank of a DIMM important to clarify exactly which Rank width field affects which clock signal: Channel Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet MCHBAR 10Ch 00h R/W 8 bits Description Reserved DIMM clock gate enable pair 5 0: Tri-state the corresponding clock pair ...
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... CASB Latency (tCL). This field is programmable on DDR2 DIMMs. The value programmed here must match the CAS Latency of every DDR2 DIMM in the system. Encoding DDR2 CL 00: 5 01: 4 10: 3 11: Reserved Reserved Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... R/W 000 b 7 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks inserted between a row activate command and a read or write command to that row. EncodingtRCD ...
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... MCHBAR 124-127h 00000000h R/W 32 bits Description Enhanced Addressing Enable (ENHADE): 0: Disabled. DRAM address map follows the standard address map. 1: Enabled. DRAM address map follows the enhanced address map. Intel Reserved Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... C1DRA2—Channel B DRAM Rank 2,3 Attribute MMIO Range: Address Offset: Default Value: Access: Size: The operation of this register is detailed in the description for register C0DRA0. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet MCHBAR 180h 00h R/W 8 bits MCHBAR ...
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... Host Bridge Registers (Device 0, Function 0) MCHBAR 18Ch 00h R/W/L 8 bits MCHBAR 18E-18Fh 0000h R/W 16 bits MCHBAR 194-197h 02483D22h R/W 32 bits MCHBAR 1A0-1A3h 4000280_00ssh R/W 32 bits MCHBAR 1A4-1A7h 00000000h R/W, R/W/L 32 bits Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... This register is Reset by PWROK only. Access & Bit Default 31:2 1 R/WC R/WC Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet MCHBAR F10-F13h 00000000h R/W 32 bits Description Reserved Enhanced Power Management Features Enable 0: Legacy power management mode 1: Reserved. Reserved ...
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... EP Link Entry 2 Address EP Link Entry 3 Description † † EP Link Entry 3 Address Link #4 (Type 1) DMI Port #1 x4 Egress Port Port #0 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Default Value Access See Section 4.3.1 R/WO, RO 01000000h R/WO, RO 0000000000000000h R/WO 02000002h R/WO, RO ...
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... Number of Link Entries This field indicates the number of link entries following the Element Self Description. This field reports 2 on Intel® 3000 chipset, and 3 on Intel® 3010 chipset (one each for the PCI Express and the DMI). Reserved Element Type: This field indicates the type of the Root Complex Element ...
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... This value is a mirror of the value in the Component ID field of all elements in this component. The value only needs to be written in one of the mirrored fields and it will be reflected everywhere that it is mirrored. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... 23:16 R/ Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description Reserved Link Type Indicates that the link points to configuration space of the integrated device which controls the root port. The link address specifies the configuration address (segment, bus, device, function) of the target root port. ...
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... Link Entry is not valid and will be ignored. 1: Link Entry specifies a valid link. EPBAR 078-07Fh 00000000_00018000h RO 64 bits Description Reserved Device Number Target for this link is PCI Express port (Device 3). Function Number Reserved § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
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... PBUSN1 19h SBUSN1 1Ah SUBUSN1 1Bh 1Ch IOBASE1 1Dh IOLIMIT1 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Table 5-1 Register Name VID1 Vendor Identification DID1 Device Identification PCI Command PCI Status RID1 Revision Identification CC1 ...
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... Link Control LSTS Link Status Slot Capabilities Slot Control Slot Status RCTL Root Control — Reserved RSTS Root Status Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Default Value Access 00h RO, R/W/C FFF0h R/W 0000h R/W FFF1h RO, R/W 0001h ...
Page 89
... CESTS 1D4–1D7h CEMSK 1D8–217h 218–21Fh PEGSSTS 220–FFFh Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Register Name — Reserved PCI Express Legacy Control Virtual Channel Enhanced Capability Header Port VC Capability Register 1 Port VC Capability Register 2 Port VC Control — ...
Page 90
... Only affects interrupts generated by the device (PCI INTA from a PME or Hot Plug event) controlled by this command register. It does not affect upstream MSIs, upstream PCI INTA-INTD asserts and de-assert messages. Fast Back-to-Back Enable (FB2B) Not Applicable or Implemented. Hardwired to 0. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 91
... R R Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description SERR Message Enable (SERRE1) This bit is an enable bit for Device 1 SERR messaging. The MCH communicates the SERRB condition by sending an SERR message to the ICH7. This bit, when set, enables reporting of non-fatal and fatal errors to the Root Complex ...
Page 92
... Indicates that an interrupt message is pending internally to the device. Only PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert and de- assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no effect on this bit. Reserved Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 93
... Default Value: Access: Size: Access & Bit Default 7:0 R Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 1 08h C0h RO 8 bits Description Revision Identification Number (RID1) Indicates the number of times that this device in this component has been “stepped” through the manufacturing process always the same as the RID values in all other devices in this component ...
Page 94
... RO 8 bits Description Secondary Bus Number (BUSN) This field is programmed by configuration software with the bus number assigned to PCI Express link. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 95
... Address Offset: Default Value: Access: Size: This register controls the CPU to PCI Express link I/O access routing based on the following formula: IO_BASE ≤ address ≤ IO_LIMIT Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 1 1Ah 00h R/W 8 bits Description ...
Page 96
... Completion status). DEVSELB Timing (DEVT) Not Applicable or Implemented. Hardwired to 0. Reserved Fast Back-to-Back (FB2B) Not Applicable or Implemented. Hardwired to 0. Reserved 66/60 MHz capability (CAP66) Not Applicable or Implemented. Hardwired to 0. Reserved Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 97
... There is no provision in the MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 1 20h FFF0h ...
Page 98
... Address Support This field indicates that the upper 32-bits of the prefetchable memory region limit address are contained in the Prefetchable Memory Base Limit Address Register (offset 2Ch). 1 26h 0000h RO, R/W 16 bits Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 99
... For the purpose of address decode address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top aligned memory block. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description Prefetchable Memory Address Limit (PMLIMIT) Corresponds to A[31:20] of the upper limit of the address range passed to PCI Express link ...
Page 100
... POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates which input of the system interrupt controller this device’s interrupt pin is connected to. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 101
... R R Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 1 3Dh 01h RO 8 bits Description Interrupt Pin single function device, the PCI Express device specifies INTA as its interrupt pin. 01h=INTA. 1 3Eh 0000h RO, R/W 16 bits Description Reserved Discard Timer SERR Enable Not Applicable or Implemented ...
Page 102
... Hardwired indicate that special initialization of this device is NOT required before generic class device driver is to use it. Auxiliary Power Source (APS) Hardwired to 0. PME Clock Hardwired indicate this device does NOT support PMEB generation. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 103
... R Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description PCI PM CAP Version Hardwired to 02h to indicate there are 4 bytes of power management registers implemented and that this device complies with revision 1.1 of the PCI Power Management Interface Specification. ...
Page 104
... Identifies the particular subsystem and is assigned by the vendor. Subsystem Vendor ID (SSVID) Identifies the manufacturer of the subsystem and is the same as the vendor ID which is assigned by the PCI Special Interest Group. 1 90h A005h RO 16 bits Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 105
... RO 000 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description Pointer to Next Capability This contains a pointer to the next item in the capabilities list which is the PCI Express capability. Capability ID Value of 05h identifies this linked list item (capability structure) as being for MSI registers ...
Page 106
... PCI Express specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration space. Capability ID Identifies this linked list item (capability structure) as being for PCI Express registers. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 107
... Default 31 4 2:0 RO 000 b Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 1 A2h 0141h RO; R/WO 16 bits Description Reserved Interrupt Message Number Not Applicable or Implemented. Hardwired to 0. Slot Implemented 0: The PCI Express Link associated with this port is connected to an integrated component or is disabled ...
Page 108
... Uncorrectable errors can result in degraded performance. Correctable Error Reporting Enable When set correctable errors will be reported. For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_CORR message is generated. 1 AAh 0000h RO 16 bits Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 109
... R/WO 010 b 14:12 R/WO 010 b Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description Reserved Transactions Pending 0: All pending transactions (including completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1: Indicates that the device has transaction(s) pending (including completions for any outstanding non-posted requests for all used Traffic Classes) ...
Page 110
... Read Completion Boundary (RCB) Hardwired indicate 64 byte. Reserved Active State PM Controls the level of active state power management supported on the given link. 00: Disabled 01: L0s Entry Supported 10: Reserved 11: L0s and L1 Entry Supported Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 111
... 9 3 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 1 B2h 1001h RO 16 bits Description Reserved Slot Clock Configuration 0: The device uses an independent clock irrespective of the presence of a reference on the connector. 1: The device uses the same physical reference clock that the platform provides on the connector ...
Page 112
... Indicates that an Attention Indicator is implemented on the chassis for this slot. Reserved Attention Button Present Indicates that an Attention Button is implemented on the chassis for this slot. The Attention Button allows the user to request hot-plug operations. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 113
... R R 2 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 1 B8h 01C0h R/W 16 bits Description Reserved Power Indicator Control Reads to this register return the current state of the Power Indicator. Writes to this register set the Power Indicator and cause the Port to send the appropriate POWER_INDICATOR_* messages ...
Page 114
... Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status Register. A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 115
... R/W 15:0 RO 0000 h Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description System Error on Fatal Error Enable Controls the Root Complex’s response to fatal errors SERR generated on receipt of fatal error. 1: Indicates that an SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port the Root Port itself ...
Page 116
... Do not forward received GPE assert/deassert messages. 1: Forward received GPE assert/deassert messages. These general GPE message can be received via the PCI Express link port from an external Intel device (i.e. Intel® 6702PXH 64-bit PCI Hub) and will be subsequently forwarded to the ICH7 (via Assert_GPE and Deassert_GPE messages on DMI). For example, an Intel® ...
Page 117
... Access & Bit Default 31: 23:8 7 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 1 104h 00000001h RO, R/WO 32 bits Description Reserved Low Priority Extended VC Count Indicates the number of (extended) Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group that has the lowest priority with respect to other VC resources in a strict-priority VC Arbitration ...
Page 118
... RO, R/W 32 bits Description VC0 Enable For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. Reserved VC0 ID Assigns the VC resource. For VC0 this is hardwired to 0 and read only. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 119
... 14:0 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description Reserved TC/VC0 Map Indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource ...
Page 120
... TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. TC0/VC1 Map Traffic Class 0 is always routed to VC0. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 121
... 15:0 RO 0005 h Note: See corresponding Egress Port Link Declaration Capability registers for diagram of Link Declaration Topology. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 1 126h 0002h RO 16 bits Description Reserved VC1 Negotiation Pending 0: The VC negotiation is complete. ...
Page 122
... Number of Link Entries Indicates the number of link entries following the Element Self Description. This field reports 01h on Intel® 3000 chipset, and 02h on Intel® 3010 chipset (to Egress port and to the other PCI Express port). Reserved Element Type Indicates the type of the Root Complex Element ...
Page 123
... Default 31: 23:16 R/ Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description Reserved Link Type Indicates that the link points to memory-mapped space (for RCRB). The link address specifies the 64-bit base address of the target RCRB. Link Valid 0: Link Entry is not valid and will be ignored. ...
Page 124
... Device Number Target for this link is PCIE1 (Device 3) Reserved 0/1/0/MMR 1C4-1C7h 00000000h RO; R/WC/S 32 bits Description Reserved Unsupported Request Error Status Reserved Malformed TLP Status Receiver Overflow Status Unexpected Completion Status Reserved Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 125
... R/W 3:0 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Description Completion Timeout Status Reserved Data Link Protocol Error Status (DLPES): The Data Link Layer Protocol Error that causes this bit to be set will also cause the Fatal Error Detected bit in Device Status[ set if not already set ...
Page 126
... Receiver Error Status (RES): Receiver Errors will be indicated due to all of the following: 8b/10b Decode Errors, Framing Errors, Lane Deskew Errors, and Elasticity Buffer Overflow/Underflow Error did Not occur 1 = Error occurred Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 127
... R/WC R/WC R/WC 5:1 0 R/WC Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 0/1/0/MMR 1D4-1D7h 00000000h RO; R/W/S 32 bits Description Reserved Replay Timer Timeout Mask 0 = Not Masked 1 = Masked Reserved Replay Number Rollover Mask 0 = Not Masked 1 = Masked Bad DLLP Mask ...
Page 128
... Next Receive Sequence Number This is the sequence number associated with the TLP that is expected to be received next. Reserved Last Acknowledged Sequence Number This is the sequence number associated with the last acknowledged TLP. § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 129
... PCICMD3 06-07h 08h 09-0Bh 0Ch 0Dh 0Eh 0F-17h 18h 19h 1Ah SUBUSN3 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Table 6-1 Register Name VID3 Vendor Identification DID3 Device Identification PCI Command PCISTS3 PCI Status RID3 Revision Identification ...
Page 130
... Device Control DSTS3 Device Status LCAP3 Link Capabilities LCTL3 Link Control LSTS3 Link Status Slot Capabilities Slot Control Slot Status Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Default Value Access — — F0h RO 00h R/W 00h RO, R/W/C FFF0h ...
Page 131
... PEGSSTS3 220–FFFh Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Register Name RCTL3 Root Control — Reserved RSTS3 Root Status — Reserved PCI Express Legacy Control ...
Page 132
... Max Link Width Hardwired to indicate x8. When Force x1 mode is enabled on this PCI Express x8 link device, this field reflects x1 (01h). Max Link Speed Hardwired to indicate 2.5 Gb/s. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet for details on the registers not ...
Page 133
... 9 3 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 3 B2h 1001h RO 16 bits Description Reserved Slot Clock Configuration 0: The device uses an independent clock irrespective of the presence of a reference on the connector. 1: The device uses the same physical reference clock that the platform provides on the connector ...
Page 134
... Reserved Element Type Indicates the type of the Root Complex Element. Value represents a root port. 3 168h 0000000000010000h R/O 64 bits Description Reserved Device Number Target for this link is PCIE0 (Device 1) Reserved § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 135
... DMILSTS 08C– 1C7h 1C8–1CBh DMIUEMSK 1CC– FFFh Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet provides a detailed bit description of the registers. Register Name DMI Virtual Channel Enhanced Capability Header DMI Port VC Capability Register 1 ...
Page 136
... Low Priority Extended VC Count (LPEVC) — Indicates that there are no additional VCs of low priority with extended capabilities. Reserved Extended VC Count Indicates that there is one additional VC (VC1) that exists with extended capabilities. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Direct Media Interface (DMI) RCRB ...
Page 137
... 14:8 7 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet DMIBAR 008h 00000001h RO 32 bits Description VC Arbitration Table Offset (ATO) Indicates that no table is present for VC arbitration since it is fixed. Reserved VC Arbitration Capability Indicates that the VC arbitration is fixed in the root complex. VC1 is highest priority and VC0 is lowest priority ...
Page 138
... Reserved DMIBAR 01Ah 0002h RO 16 bits Description Reserved VC Negotiation Pending (NP) When set, indicates the virtual channel is still being negotiated with ingress ports. Reserved Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Direct Media Interface (DMI) RCRB ...
Page 139
... R/W 001 b 23:20 19:17 R 16:8 7:1 R Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet DMIBAR 01Ch 00008001h RO 32 bits Description Reserved Reject Snoop Transactions (RTS) All snoopable transactions on VC1 are rejected. This VC is for isochronous transfers only. Reserved Port Arbitration Capability (PAC) Indicates the port arbitration capability is time-based WRR of 128 phases ...
Page 140
... Indicates that L0s is supported on DMI. Maximum Link Width (MLW) Indicates the maximum link width is 4 ports. Maximum Link Speed (MLS) Indicates the link speed is 2.5 Gb/s. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Direct Media Interface (DMI) RCRB ...
Page 141
... Access & Bit Default 15: Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet DMIBAR 088h 0000h R/W 16 bits Description Reserved Extended Synch (ES) When set, forces extended transmission of FTS ordered sets when exiting L0s prior to entering L0 and extra TS1 sequences at exit from L1 prior to entering L0. ...
Page 142
... DMIUESTS Register. Access & Bit Default 31:21 20 R/W 19:0 142 0/0/0/DMIBAR 1C8-1CBh 00000000h RO; R/W/S; 32 bits Description Reserved Unsupported Request Error Mask 0: Not Masked 1: Masked Reserved § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Direct Media Interface (DMI) RCRB ...
Page 143
... E. IFPBAR - Any write to this window will trigger a flush of the MCH’s Global Write Buffer to let software guarantee coherency between writes from an isochronous agent and writes from the CPU (4 KB window). Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 143 ...
Page 144
... The only peer-to-peer cycles allowed below the top of memory (register TOLUD) are DMI to PCI Express VGA range writes. Figure 8-1 represents system memory address map in a simplified form. 144 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet System Address Map ...
Page 145
... Main Memory Address Range 4 GB Address Range decoded to DMI) TOLUD Main Memory Address Range 1 MB Legacy Address 0 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet PCI Memory Device 1 PMUbase/PMUlimit Remap Base/Limit Device 0 Bars Device 0 PCI Memory (EPBAR, GGC MCHBAR, ...
Page 146
... sections (total of 4 sections) – Extended System BIOS Area • 960 KB – Memory – System BIOS Area Figure 8-2. Microsoft MS-DOS* Legacy Address Range 146 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet System Address Map ...
Page 147
... MCH and are subtractively decoded to ISA space. Memory that is disabled is not remapped. Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Table 8-1). Each segment can be assigned one of four Read/Write 147 ...
Page 148
... Attributes Attributes WE RE Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet System Address Map Comments Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Comments BIOS Extension BIOS Extension BIOS Extension ...
Page 149
... Main Memory Address Range F_FFFF_FFFFh Contains: Dev 0, 1, BARS & ICH/PCI Ranges 0_0100_0000h 0_00F0_0000h 0_0010_0000h Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Table 8-3) extends from the top of physical memory FLASH APIC PCI Memory Range TSEG (1MB/2MB/8MB, optional) ...
Page 150
... Attributes R/W Available System Memory 62 MB SMM Mode Only - CPU TSEG Address Range & Pre-allocated Memory Reads R/W Pre-allocated VGA memory. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet System Address Map Comments ...
Page 151
... The exceptions listed above for PCI Express ports MUST NOT overlap with APCI Configuration, FSB Interrupt Space and High BIOS Address Range. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Table 8-4), from the top of physical memory ...
Page 152
... PCI Express* Possible address range Configuration Space (Not fixed – 512 MB Programmable DMI Interface windows, PCI (subtractive decode) Express* Port could be here TOLUD Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet System Address Map Optional HSEG FEDA_0000h to FEDB_FFFFh ...
Page 153
... TOLUD register is restricted memory (A[31:27]), but the MCH can support GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOM register helps identify the address range in between the 4 GB boundary and the top of Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 153 ...
Page 154
... There is a device 0 register, PCIEXBAR, that defines the base address for the 256 MB block of addresses below the top of addressable memory (currently 4 GB) for the configuration space associated with all devices and functions that are potentially a part 154 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet System Address Map ...
Page 155
... The above 1 MB solutions require changes to compatible SMRAM handlers’ code to properly execute above 1 MB. Note: DMI and PCI Express masters are not allowed to access the SMM space. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 155 ...
Page 156
... TOLUD High Enable TSEG Enable Compatible (C) TSEG_EN Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet System Address Map DRAM Space (DRAM) 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh (TOLUD-TSEG) to TOLUD High (H) TSEG (T) Range Range Range Disable Disable Disable Enable Disable ...
Page 157
... Within the host bridge the MCH contains two internal registers in the CPU I/O space, Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA). These locations are used to implement a configuration space access mechanism. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet CPU in SMM D_CLS D_OPEN ...
Page 158
... PCI Express. Subsequent decoding of regions mapped to PCI Express or the DMI depends on the Legacy VGA configurations bits (VGA Enable & MDAP) in the LAC register (Device 0). 158 § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet System Address Map ...
Page 159
... HDINV# signal will be asserted and the data will be inverted prior to being driven on the bus. Whenever the CPU or the MCH receives data it monitors HDINV[3:0]# to determine if the corresponding data segment should be inverted. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 159 ...
Page 160
... MB Cumulative Top Channel A Address in Population Channel 1280 MB 256 MB 1280 MB 512 MB 1024 MB 512 MB 512 MB Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Functional Description Table 9-1 and Table 9-2. Cumulative Top Channel B Address in Population Channel 2560 MB 256 MB 2560 MB ...
Page 161
... The DRT register defines the timing parameters for all devices in a channel. The BIOS programs this register with “least common denominator” values after reading the SPD registers of each DIMM in the channel. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet single channel dual channel interleaved channels don’ ...
Page 162
... In Dual Channel Asymmetric mode, any DIMM slot may be populated in any order. In Dual Channel Interleaved mode, any DIMM slot may be populated in any order, but the total memory in each channel must be the same. 162 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Functional Description ...
Page 163
... Note ‘bank’ select bit c - ‘column’ address bit r - ‘row’ address bit Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet # of Row # of Column # of Bank Address Bits Address Bits Address Bits specify the host interface to memory interface address of this document ...
Page 164
... The MCH drives out the required ODT signals, based on memory configuration and which rank is being written to or read from, to the DRAM devices on a targeted DIMM rank to enable or disable their termination resistance. 164 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Functional Description ...
Page 165
... PCIE0. Device 3 contains the control registers for PCIE1. The PCI Express links are mapped through separate PCI-PCI bridge structures. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Section 9.3.8 are for Intel® 3010 chipset only. ...
Page 166
... Secondary Slot (PCIE0) (PCIE1) None x16 Primary (PCIE0) x1, x4, x8 Primary (PCIE0) Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Functional Description MCH PCI Compatible RCRB for Host Bridge Egress Port Device (access to Main (Device 0) Memory) RCRB for DMI ...
Page 167
... As shown in the following figure, the device controls associated with the lanes also changes such that the same logical lanes are always controlled by the same device. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Secondary Slot ...
Page 168
... PRSNT1# PRSNT2# PRSNT2 Secondary (PCIE1) DPEN (Secondary Slot (Devs 1 & 3 Enabled Secondary (Dev 3 Enabled) Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Functional Description MCH 0 15 Dev 1 Dev 3 Dev 3 Dev DPEN# PRIPRSNT# DPEN (Secondary Slot) 1 x16 (Dev 1 Enabled) ...
Page 169
... If the performance peer path is disabled and a write occurs to that range then the central peer path state controls whether that write will be completed to the intended device (enabled) or the write becomes unsupported (disabled). Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet nd PCI Express port 169 ...
Page 170
... This time is measured from when an upstream write starts on the external pins until the start of the downstream write is seen on the external pins. 170 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Functional Description ...
Page 171
... Advanced Err or Reporting registers which are NOT implemented. Advanced Err or Reporting re gisters which are impleme nted (which will not be exposed as a capability). Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Poisoned T LP Par ity Error Response Enable Bridge Contr ol (received) ...
Page 172
... PCI Express PLL – Generates all PCI Express related clocks, including the Direct Media Interface that connects to the ICH7. This PLL uses the 100 MHz (GCLK reference. For system clock diagram, please refer to the latest Intel® 3000 and 3010 Chipset Platform Design Guide. 172 § ...
Page 173
... Note: 1. Possible damage to the MCH may occur if the MCH temperature exceeds 150 °C. Intel does not guarantee functionality for parts that have exceeded temperatures above 150 °C due to spec violation. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet ...
Page 174
... Max currents cannot occur simultaneously on all interfaces. cc 174 Signal Names Min VTT VCC VCC_EXP VCCA_3GBG VCC2 VCCA_EXPPLL VCCA_HPLL Parameter Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Electrical Characteristics Typ Max Unit Notes 0.9 A 1,4,5 8.9 A 2,3,4,5 1.5 ...
Page 175
... PCI Express Present Strap (Intel® 3010 Chipset only) Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details. The MCH integrates most GTL+ termination resistors. ...
Page 176
... SODT_A[3:0], SODT_B[3:0], SCKE_A[3:0], SCKE_B[3:0], SCS_A[3:0]#, SCS_B[3:0]#, SCLK_A[5:0], SCLK_A[5:0]#, SCLK_B[5:0], SCLK_B[5:0]# SMVREF[1:0] EXTTS# RSTIN#, PWROK ICH_SYNC# HCLKN, HCLKP, GCLKP, GCLKN VTT VCC_EXP VCCSM VCC_SMPLL VCC VCC2 VCCA_HPLL, VCCA_EXPPLL VCCA_3GBG Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Electrical Characteristics Notes ...
Page 177
... V (h) DDR2 Input High Voltage IH(AC) V (h, i) DDR2 Output Low Voltage OL V (h, i) DDR2 Output High Voltage OH Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Parameter Min 1.7 1.425 1.425 0.9975 1.425 2.375 1.425 2.375 0.63 x VTT –2% 0.22 x VTT – ...
Page 178
... Havg 0.700) 1 2.0 4.690 measured by the oscilloscope. H § Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Electrical Characteristics Nom Max Unit Notes ±20 µA 5 ±550 µA 6 6 100 120 Ω ...
Page 179
... Some balls marked as reserved (RSV) are used in XOR testing. See details. Note: Some balls marked as reserved (RSV) can be used as test points. These are marked as RSV_TPx. Note: Balls that are listed as NC are No Connects. Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Section 12 for 179 ...
Page 180
... HD55# HD57# HD60# HD59# VSS VSS HD26# HD28# HD58# HD62# HDINV3# HDSTBN3# VSS VSS HD49# HDINV1# Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ballout and Package Information SMA _A 4 VCCSM SCKE_A1 VCCSM VCCSM SBS_A2 VCCSM S MA_A2 S MA_A8 SMA_A11 ...
Page 181
... VCC_EXP VSS VSS VCC_EXP PM_BMBUSY# PRIPRSNT# VCC_EXP VCC_EXP VCCA_SMPLL VSS VCC2 VCC_EXP VCC_EXP VCCA_EXPPLL VCC_EXP VC CA_3GBG Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet 8 VSS VCCSM VCCSM SDQS_A2# VSS VSS VCCSM SDQ_A18 SDQ_A23 SDQ_A16 SDQ_A11 SCKE_B3 SDQ_A19 SDQS_A2 ...
Page 182
... Note: Throughout this chapter and the next, the symbol “†” indicates a signal that is Reserved on the Intel® 3000 chipset but is used by Intel® 3010 chipset. Table 11-1. MCH Ballout Table – Sorted by Signal Name Ball Signal Name ...
Page 183
... HD14# F43 HD15# F37 HD16# E37 HD17# J35 HD18# D39 HD19# P42 HD2# C41 HD20# Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ball Signal Name Ball B39 HD21# C32 B40 HD22# D32 H34 HD23# B30 C37 HD24# ...
Page 184
... SCLK_A2# BB31 SCLK_A3 BA31 SCLK_A3# AY7 SCLK_A4 BC6 SCLK_A4# AH43 SCLK_A5 AH40 SCLK_A5# Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ballout and Package Information Ball Signal Name AM29 SCLK_B0 AM27 SCLK_B0# AJ9 SCLK_B1 AJ11 SCLK_B1# AL38 SCLK_B2 ...
Page 185
... SDQ_A47 AL39 SDQ_A48 AK40 SDQ_A49 AR3 SDQ_A5 AF39 SDQ_A50 AE40 SDQ_A51 AL41 SDQ_A52 AL42 SDQ_A53 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ball Signal Name Ball AF41 SDQ_A54 AM31 AF42 SDQ_A55 AP27 AD40 SDQ_A56 AU27 AD43 SDQ_A57 ...
Page 186
... AA27 VCC AF29 AA29 VCC AF30 AB17 VCC AG19 AB18 VCC AG20 AB20 VCC AG30 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ...
Page 187
... VCC U18 VCC U19 VCC U20 VCC U21 VCC U22 VCC U23 VCC U24 VCC Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ball Signal Name Ball U25 VCC D16 U26 VCC D17 U27 VCC E13 U30 VCC ...
Page 188
... AD13 VSS AG12 AD14 VSS AG13 AD19 VSS AG14 AD2 VSS AG15 AD21 VSS AG17 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...
Page 189
... VSS AL21 VSS AL23 VSS AL24 VSS AL26 VSS AL27 VSS AL29 VSS AL31 VSS Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ball Signal Name Ball AL33 VSS AT12 AL35 VSS AT17 AL37 VSS AT18 AL43 VSS ...
Page 190
... VSS R31 K39 VSS R34 K5 VSS R37 K6 VSS R39 K7 VSS L12 VSS L2 VSS L24 VSS Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Name VSS VSS VSS VSS VSS VSS VSS M3 VSS VSS VSS M5 VSS M8 VSS M9 VSS ...
Page 191
... V34 VSS V36 VSS V37 VSS V38 VSS V39 VSS V43 VSS V5 VSS V8 VSS Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ball Signal Name Ball W20 VSS B25 W22 VSS B26 W24 VSS C23 W26 VSS C25 ...
Page 192
... AC12 EXP_COMPO AD13 AC13 VSS AD14 AC14 VSS AD15 AC15 VCC AD17 AC17 VCC AD18 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Name VSS VCC VSS VSS VCC VSS VCC VSS VCC VCC VCC VCC VSS ...
Page 193
... VCC AE22 VSS AE23 VCC AE24 VSS AE25 VCC AE26 VCC AE27 VCC AE3 RSTIN# Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ball Signal Name Ball AE4 VSS AG10 AE40 SDQ_A51 AG11 AE41 SDQ_A61 AG12 AE42 SDQ_A60 ...
Page 194
... AL7 SDQ_B15 AN21 AL8 VSS AN23 AL9 SDQ_B14 AN24 AM10 SDQ_B16 AN26 AM11 SDQ_B31 AN27 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Name SDQ_A24 SDQ_A28 SDQ_A31 SCB_A4 SDQS_B0 SCB_A5 SCB_B4 SCB_B1 SCB_B0 SCB_B3 SCLK_B0# SCLK_B0 SDQS_B0# ...
Page 195
... SDQ_B17 AP7 VSS AP8 SDM_B2 AP9 SDQ_B22 AR1 VSS AR10 SDQS_B3 AR12 SDQS_B3# AR13 SDQ_B27 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ball Signal Name Ball AR15 VSS AU12 AR17 SDQ_A27 AU13 AR18 SCB_A1 AU15 AR2 SDQ_A0 ...
Page 196
... B21 VSS BA31 B22 VSS BA32 B23 VSS BA34 B24 VTT BA35 B25 VTT BA37 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Signal Name VTT HSWING VSS B3 NC HD62# HD58# HDINV3# VSS HD28# HD26# HDSTBN3# VSS HD21# ...
Page 197
... SODT_A2 BB38 VCCSM BB39 VSS BB4 SDQS_A1# BB40 SRAS_B# BB41 VSS BB42 VCCSM BB43 NC Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ball Signal Name Ball BB5 SDQS_A1 C34 BB6 VSS C35 BB7 SDQ_A15 C37 BB9 SDQ_A11 C39 ...
Page 198
... VSS G6 EXP_RX0P7 G7 VSS G9 VSS H10 EXP_RX0N4 H12 VSS H13 EXP_RX0N2 H15 VCC_EXP Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ballout and Package Information Ball Signal Name H17 VCC H18 VCC H20 XORTEST H21 BSEL1 H23 VTT H24 ...
Page 199
... L17 VCC L18 VCC L2 VSS L20 BSEL2 L21 RSV_TP4 L23 VTT L24 VSS L26 VSS Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ball Signal Name L27 HD40# L29 VSS L31 VSS L32 HD30# L4 EXP_TX1P2 † L40 HD6# † ...
Page 200
... U9 VCC_EXP † V1 VSS V10 EXP_RX1N7 † V11 VSS V12 VCC_EXP V13 VCC_EXP Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet Ballout and Package Information Ball Signal Name V14 VCC_EXP V15 VCC V17 VCC V18 VCC V19 VCC V2 EXP_TX1N6 † ...