NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 110

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.39
110
LCTL—Link Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Allows control of PCI Express link.
11:10
15:7
9:4
3:0
1:0
Bit
Bit
6
5
4
3
2
3000 chipset)
3010 chipset)
Access &
08 h (Intel®
10 h (Intel®
Default
Access &
Default
00 b
R/W
R/W
R/W
R/W
0 b
0 b
0 b
RO
0 b
11 b
RO
RO
RO
1 h
Reserved
Common Clock Configuration
0: Indicates that this component and the component at the opposite end of this Link
1: Indicates that this component and the component at the opposite end of this Link
Components utilize this common clock configuration information to report the
correct L0s and L1 Exit Latencies.
Retrain Link
0: Normal operation
1: Full Link retraining is initiated by directing the Physical Layer LTSSM from L0,
This bit always returns 0 when read. This bit is cleared automatically (no need to
write a 0).
Link Disable
0: Normal operation
1: Link is disabled. Forces the LTSSM to transition to the Disabled state (via
Link retraining happens automatically on 0 to 0 transition, just like when coming out
of reset. Writes to this bit are immediately reflected in the value read from the bit,
regardless of actual Link state.
Read Completion Boundary (RCB)
Hardwired to 0 to indicate 64 byte.
Reserved
Active State PM
Controls the level of active state power management supported on the given link.
00:
01:
10:
11:
Active State Link PM Support
L0s & L1 entry supported.
Max Link Width
Intel® 3000 chipset only: Hardwired to indicate x8.
Intel® 3010 chipset only: Hardwired to indicate x16.
When Force x1 mode is enabled on this PCI Express link device, this field reflects
x1 (01h).
Max Link Speed
Hardwired to indicate 2.5 Gb/s.
are operating with asynchronous reference clock.
are operating with a distributed common reference clock.
L0s, or L1 states to the Recovery state.
Recovery) from L0, L0s, or L1 states.
1
B0h
0000h
RO, R/W
16 bits
Disabled
L0s Entry Supported
Reserved
L0s and L1 Entry Supported
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Host-PCI Express Bridge Registers (D1:F0)
Description