NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 149

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

System Address Map
8.1.6
8.2
Figure 8-3.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Programmable Attribute Map (PAM) Memory Area Details
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory
Area.
The MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there will normally not be
IWB cycles targeting DMI.
However, DMI becomes the default target for CPU and DMI originated accesses to
disabled segments of the PAM region. If the MTRRs covering the PAM regions are set to
WB or RC it is possible to get IWB cycles targeting DMI. This may occur for DMI
originated cycles to disabled PAM regions.
For example, say that a particular PAM region is set for “Read Disabled” and the MTRR
associated with this region is set to WB. A DMI master generates a memory read
targeting the PAM region. A snoop is generated on the FSB and the result is an IWB.
Since the PAM region is “Read Disabled” the default target for the Memory Read
becomes DMI. The IWB associated with this cycle will cause the MCH to hang.
Main Memory Address Range (1 MB to TOLUD)
This address range (see
that is permitted to be accessible by the MCH (as programmed in the TOLUD register).
All accesses to addresses within this range will be forwarded by the MCH to the DRAM
unless they fall into the optional TSEG or optional ISA Hole.
Main Memory Address Range
Contains:
Dev 0, 1, BARS
& ICH/PCI Ranges
F_FFFF_FFFFh
0_00F0_0000h
0_0100_0000h
0_0010_0000h
Table
0h
8-3) extends from 1 MB to the top of physical memory
TSEG
DOS Compatibility Memory
PCI Memory Range
ISA Hole (optional)
(1MB/2MB/8MB, optional)
Main Memory
Main Memory
FLASH
APIC
TOLUD
64GB
16MB
15MB
1MB
0MB
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