NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 52

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.11
4.1.12
Note:
52
CAPPTR—Capabilities Pointer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
The CAPPTR register provides the offset that is the pointer to the location of the first
device capability in the capability list.
EPBAR—Egress Port Base Address (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the Egress Port MMIO Configuration space. There is no
physical memory within this 4 KB window that can be addressed. The 4 KB space
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space.
On reset, this register is disabled and must be enabled by writing a 1 to EPBAREN.
31:12
11:1
7:0
Bit
Bit
0
Access &
Access &
00000 h
Default
Default
E0 h
R/W
R/W
RO
0b
Pointer to the Offset of the First Capability ID Register Block:
In this case the first capability is the product-specific Capability Identifier (CAPID0).
Egress Port MMIO Base Address:
This field corresponds to bits 31 to 12 of the base address Egress Port MMIO
configuration space.
BIOS will program this register resulting in a base address for a 4 KB block of
contiguous memory address space. This register ensures that a naturally aligned
4 KB space is allocated within total addressable memory space of 8 GB.
System software uses this base address to program the MCH MMIO register set.
Reserved
EPBAR enable (EPBAREN):
0: EPBAR is disabled and does not claim any memory
1: EPBAR memory mapped accesses are claimed and decoded appropriately
0
34h
E0h
RO
8 bits
0
40-43h
00000000h
RO
32 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description
Description