NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 18

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

1.3.3
1.3.4
18
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the MCH and the
ICH. This high-speed interface integrates advanced priority-based servicing allowing for
concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software transparent permitting current and legacy software to operate
normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the ICH7 supports two virtual channels on DMI: VC0 and VC1. These two
channels provide a fixed arbitration scheme where VC1 is always the highest priority.
VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be
specifically enabled and configured at both ends of the DMI link (i.e., the ICH7 and
MCH).
Configuration registers for DMI, virtual channel support, and DMI active state power
management (ASPM) are in the RCRB space in the MCH Register Description. Features
of the DMI include:
PCI Express* Interface(s)
The PCI Express port(s) supports a bi-directional transfer rate of 2.5 Gb/s for a
theoretical bandwidth of 8 GB/s when in x16 mode. Features of the PCI Express port
include:
• Supports opportunistic refresh.
• In dual channel mode, the MCH supports 64 simultaneously open pages.
• SPD (Serial Presence Detect) scheme for DIMM detection support.
• Supports configurations defined in the JEDEC DDR2 DIMM specification only.
• Supports a burst length of 8 for single-channel and dual-channel interleaved and
• Supports Enhanced Memory Interleave.
• A chip-to-chip connection interface to ICH7
• 2 GB/s point-to-point DMI interface to ICH7 (1 GB/s each direction)
• 100 MHz reference clock (shared with PCI Express interface)
• 32-bit downstream addressing
• APIC and MSI interrupt messaging support. Will send Intel-defined “End Of
• Message Signaled Interrupt (MSI) messages
• SMI, SCI and SERR event notification
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
• PCI Express port fully compatible to the PCI Express Base Specification, Revision
• Intel® 3000 chipset supports one x8 PCI Express port
• Intel® 3010 chipset supports two x8 PCI Express ports, or one x16 PCI Express
• Base PCI Express frequency of 2.5 Gb/s only
asymmetric operating modes.
Interrupt” broadcast message when initiated by the CPU.
DMA, floppy drive, and LPC bus masters
1.0a.
port.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Introduction