NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 62

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.27
62
LAC—Legacy Access Control (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This 8-bit register controls a fixed DRAM hole from 15-16 MB.
6:1
Bit
7
0
Access &
Default
R/W
R/W
0 b
0 b
Hole Enable (HEN): This field enables a memory hole in DRAM space. The DRAM
that lies "behind" this space is not remapped.
0: No memory hole.
1: Memory hole from 15 MB to 16 MB.
Reserved
MDA Present (MDAP):
This bit works with the VGA Enable bits in the BCTRL register of Device 1 or 3 to
control the routing of CPU initiated transactions targeting MDA compatible I/O and
memory address ranges. This bit should not be set if device 1's VGA Enable bit is
not set. Software must insure the setting of the VGA Enable bits in Device 1 and
Device 3 are mutually exclusive.
If device 1's VGA enable bit is not set, then accesses to I/O address range x3BCh-
x3BFh are forwarded to the DMI.
If the VGA enable bit is set and MDA is not present, then accesses to I/O address
range x3BCh-x3BFh are forwarded to PCI Express if the address is within the
corresponding IOBASE and IOLIMIT, otherwise they are forwarded to the DMI.
MDA resources are defined as the following:
Memory: 0B0000h - 0B7FFFh
I/O:3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
Any I/O reference that includes the I/O locations listed above, or their aliases, will
be forwarded to the DMI even if the reference includes I/O locations not listed
above.
The following table shows the behavior for all combinations of MDA and VGA:
VGA and MDA memory cycles can only be routed across the PCI Express lanes
when MAE (PCICMD1[1]) is set.
VGA and MDA I/O cycles can only be routed across the PCI Express lanes if IOAE
(PCICMD1[0]) is set.
0
97h
00h
R/W
8 bits
(Including ISA address aliases, A [15:10] are not used in decode)
VGAEN
0
0
1
1
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
MDAP
0
1
0
1
Host Bridge Registers (Device 0, Function 0)
All references to MDA an dVGA space are
routed to the DMI
Invalid combination
Reserved
MDA references are routed to the DMI
Description
Description