NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 168
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NH82801GR S L8FY
Manufacturer Part Number
NH82801GR S L8FY
Description
Manufacturer
Intel
Datasheet
1.NH82801GR_S_L8FY.pdf
(218 pages)
Specifications of NH82801GR S L8FY
Lead Free Status / RoHS Status
Compliant
- Current page: 168 of 218
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Figure 9-3.
9.3.4
Table 9-7.
168
Lane Reversal (Dual PCI Express Configuration Example)
PCI Express Straps (Intel® 3010 chipset only)
There is no dynamic detection so straps are required to indicate the desired
configuration to the MCH. Two straps are defined in order to support Dual PCI Express
functionality. Each will connect to the PRSNT2# pin of a PCI Express connector and will
indicate whether a PCI Express card is present in the corresponding slot. Polarity needs
to match as the PCI Express specification defines how the Present Detect signals work
(PRSNT2# asserted low to indicate presence).
DPEN# is the low asserted motherboard signal indicating Dual PCI Express Enable.
PRIPRSNT# is the low asserted motherboard signal indicating a PCI Express card is
Present in the Primary slot.
Strap Combinations
The PRSNT2# connector signals (and corresponding straps) are pulled low when a PCI
Express card is present in the slot. When the slot is empty, the PRSNT2# connector
signals (and corresponding straps) are pulled high.
PRIPRSNT# = 0
PRIPRSNT# = 0
(Primary Slot)
(Primary Slot)
15
(PCIE0)
0
15
Primary
Always
Dev 1
15
15
0
PRSNT1#
PRSNT2#
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
(Devs 1 & 3 Enabled)
1 x8 in Secondary
(Secondary Slot)
(Dev 3 Enabled)
Secondary
DPEN# = 0
15
0
15
(PCIE1)
Always
Dev 3
2 x8
15
15
0
PRSNT1#
PRSNT2#
No PCI Express cards in slots
Dev 1
DPEN# PRIPRSNT#
Dev 3
0
15
MCH
(Secondary Slot)
(Dev 1 Enabled)
Dev 3
Dev 1
DPEN# = 1
Functional Description
15
0
1 x16
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