NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 83

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.3.1
4.3.2
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
EPESD—EP Element Self Description
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register provides information about the root complex element containing this Link
Declaration Capability.
EPLE1D—EP Link Entry 1 Description
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
This register provides the first part of a Link Entry, which declares an internal link to
another Root Complex Element.
31:24
23:16
31:24
23:16
15:8
7:4
3:0
Bit
Bit
3000 chipset)
3010 chipset)
02 h (Intel®
03h (Intel®
Access &
Access &
Default
Default
R/WO
01 h
00 h
R/WO
RO
00 h
00 h
01h
RO
RO
RO
Target Port Number
This field specifies the port number associated with the element targeted by this link
entry (DMI). The target port number is with respect to the component that contains
this element as specified by the target component ID.
Target Component ID
This field identifies the physical or logical component that is targeted by this link
entry. A value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Port Number
This field specifies the port number associated with this element with respect to
the component that contains this element.
Value of 00 h indicates to configuration software that this is the default egress
port.
Component ID
This field identifies the physical component that contains this Root Complex
Element. Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Number of Link Entries
This field indicates the number of link entries following the Element Self
Description. This field reports 2 on Intel® 3000 chipset, and 3 on Intel® 3010
chipset (one each for the PCI Express and the DMI).
Reserved
Element Type: This field indicates the type of the Root Complex Element. Value
of 1h represents a port to system memory
EPBAR
044-047h
00000201h (Intel® 3000); 00000301h (Intel® 3010 chipset)
RO, R/WO
32 bits
EPBAR
050-053h
01000000h
RO, R/WO
32 bits
Description
Description
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