NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 48

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.3
48
PCICMD—PCI Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Since MCH Device 0 does not physically reside on Primary PCI bus, many of the bits are
not implemented.
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Access &
Default
R/W
RO
0 b
0 b
RO
0 b
RO
0 b
RO
0 b
RO
0 b
RO
1 b
RO
1 b
RO
0 b
Reserved
Fast Back-to-Back Enable (FB2B):
Not implemented. Hardwired to 0. This bit controls whether or not the master can
do fast back-to-back write. Since device 0 is strictly a target, this bit is not
implemented.
SERR Enable (SERRE):
This bit is a global enable bit for Device 0 SERR messaging. The MCH does not have
an SERR signal. The MCH communicates the SERR condition by sending an SERR
message over DMI to the ICH7.
1: Enable. The MCH is enabled to generate SERR messages over DMI for specific
Device 0 error conditions that are individually enabled in the ERRCMD register. The
error status is reported in the ERRSTS, and PCISTS registers.
0: Disable. The SERR message is not generated by the MCH for Device 0.
Note:
Address/Data Stepping Enable (ADSTEP):
Not implemented. Hardwired to 0. Address/data stepping is not implemented in the
MCH.
Parity Error Enable (PERRE):
Not implemented. Hardwired to 0. PERR# is not implemented by the MCH.
VGA Palette Snoop Enable (VGASNOOP):
Not implemented. Hardwired to 0. Writes to this bit position have no effect.
Memory Write and Invalidate Enable (MWIE):
Not implemented. Hardwired to 0. The MCH will never issue memory write and
invalidate commands.
Reserved
Bus Master Enable (BME):
Hardwired to 1. The MCH is always enabled as a master.
Memory Access Enable (MAE):
Hardwired to 1. The MCH always allows access to main memory.
I/O Access Enable (IOAE):
Not implemented. Hardwired to 0.
0
04-05h
0006h
RO, R/W
16 bits
This bit only controls SERR messaging for the Device 0. Device 1 (and
Device 3 for Intel® 3010 chipset) has its own SERRE bits to control error
reporting for error conditions occurring in that device. The control bits are
used in a logical OR manner to enable the SERR DMI message mechanism.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description