NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 98

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.17
5.1.18
98
PMBASE1—Prefetchable Memory Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register in conjunction with the corresponding Upper Base Address register
controls the CPU to PCI Express link prefetchable memory access routing based on the
following formula:
The upper 12 bits of this register are read/write and correspond to address bits A
[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A [39:32] of the 40-bit address. The
configuration software must initialize this register. For the purpose of address decodes
address bits A [19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1 MB boundary.
PMLIMIT1—Prefetchable Memory Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register in conjunction with the corresponding Upper Limit Address register
controls the CPU to PCI Express link prefetchable memory access routing based on the
following formula:
The upper 12 bits of this register are read/write and correspond to address bits A
[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A [39:32] of the 40-bit address. The
configuration software must initialize this register. For the purpose of address decodes
address bits A [19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block. Note that
15:4
15:4
3:0
3:0
Bit
Bit
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
PREFETCHABLE_MEMORY_BASE ≤ Address ≤ PREFETCHABLE_MEMORY_LIMIT
Access &
Access &
Default
Default
000 h
FFF h
R/W
R/W
RO
1h
Memory Address Limit (MLIMIT)
Corresponds to A[31:20] of the upper limit of the address range passed to PCI
Express link.
Reserved
Prefetchable Memory Base Address (MBASE)
Corresponds to A[31:20] of the lower limit of the memory range that will be passed
to PCI Express link.
64-bit Address Support
This field indicates that the upper 32-bits of the prefetchable memory region limit
address are contained in the Prefetchable Memory Base Limit Address Register
(offset 2Ch).
1
24h
FFF1h
RO, R/W
16 bits
1
26h
0000h
RO, R/W
16 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Host-PCI Express Bridge Registers (D1:F0)