NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 178

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Table 10-5. DC Characteristics (Sheet 2 of 2)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. V
11. For all noise components 20 MHz, the sum of the DC voltage and AC noise component must be within the specified DC min/
178
I
I
C
1.5V PCI Express Interface 1.0a
V
V
Z
V
V
Clocks, Reset, and Miscellaneous Signals
V
V
I
C
V
V
V
V
V
C
V
V
I
C
Leak
Leak
LEAK
LEAK
TX-DIFF P-P
TX_CM-ACp
TX-DIFF-DC
RX-DIFF p-p
RX_CM-ACp
IL
IH
IL
IH
CROSS(abs)
CROSS(rel)
CROSS
IL
IH
I/O
IN
IN
IN
Determined with 2x MCH DDR2 Buffer Strength Settings into a 50 Ω to 0.5 x VCCSM test load.
Specified at the measurement point into a timing and voltage compliance test load as shown in Transmitter compliance eye
diagram of PCI Express specification and measured over any 250 consecutive TX Uls.
Specified at the measurement point and measured over any 250 consecutive Uls. The test load shown in Receiver compliance
eye diagram of PCI Express spec should be used as the RX device when taking measurements.
This is the DC voltage supplied at the MCH and is inclusive of all noise up to 20 MHz. Any noise above 20MHz at the MCH
generated from any source other than the MCH itself may not exceed the DC voltage range of 1.8V ± 100 mV.
Applies to the pin to VCC or VSS leakage current for the SDQ_A[63:0], SDQ_B[63:0], SCB_A[7:0], and SCB_B[7:0] signals.
Applies to the pin to pin leakage current between the SDQS_A[8:0], SDQS_A[8:0]#, SDQS_B[8:0]#, and SDQS_B[8:0]#
signals.
Crossing Voltage is defined as the instantaneous voltage value when the rising edge is equal to the falling edge.
V
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
max operating range.
Symbol
Havg
CROSS
is the statistical average of the V
is defined as the total variation of all crossing voltages as defined in note 7.
Signal
Group
(h, i)
(h)
(h)
(e)
(e)
(k)
(k)
(k)
(k)
(n)
(n)
(n)
(n)
(n)
(n)
(f)
(f)
(f)
(l)
(l)
(l)
(l)
Input Leakage Current
Input Leakage Current
DDR2 Input/Output Pin
Capacitance
Differential Peak to Peak Output
Voltage
AC Peak Common Mode Output
Voltage
DC Differential TX Impedance
Differential Peak to Peak Input
Voltage
AC Peak Common Mode Input
Voltage
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
Input Low Voltage
Input High Voltage
Absolute Crossing Point
Relative Crossing Point
Range of Crossing Points
Input Capacitance
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
Parameter
H
measured by the oscilloscope.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
0.250 + 0.5 *
(V
-0.150
0.700)
0.800
0.175
0.660
0.250
4.690
Min
Havg
3.0
2.0
3.0
2.0
80
§
1
–
0.700
Nom
100
0
0.550 + 0.5 *
(V
Electrical Characteristics
0.770)
0.850
0.550
0.140
5.370
±550
±100
Max
±20
120
150
Havg
±20
6.0
1.2
1.2
0.8
6.0
0.8
20
3
–
Unit
mV
mV
µA
µA
pF
μA
μA
pF
pF
pF
V
Ω
V
V
V
V
V
V
V
V
V
V
0<Vin<
VCC3_
3
Notes
7, 9
8, 9
10
5
6
2
3