NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 59

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.1.21
4.1.22
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
PAM1—Programmable Attribute Map 1 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C0000h-0C7FFFh.
PAM2—Programmable Attribute Map 2 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C8000h-0CFFFFh.
7:6
5:4
3:2
1:0
Bit
7:6
5:4
3:2
1:0
Bit
Access &
Default
R/W
00 b
R/W
00 b
Access &
Default
00 b
00 b
R/W
R/W
Reserved
0C4000-0C7FFF Attribute (HIENABLE): This field controls the steering of read and
write cycles that address the BIOS area from 0C4000 to 0C7FFF.
Reserved
0C0000-0C3FFF Attribute (LOENABLE): This field controls the steering of read and
write cycles that address the BIOS area from 0C0000 to 0C3FFF.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
0CC000-0CFFFF Attribute (HIENABLE):
Reserved
0C8000-0CBFFF Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0C8000 to 0CBFFF.
0
91h
00h
R/W
8 bits
0
92h
00h
R/W
8 bits
DMI.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
DMI.
DMI.
Description
Description
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