NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 77

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.2.10
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
C0DRC0—Channel A DRAM Controller Mode 0
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
31:30
28:11
10:8
6:4
2:0
Bit
Bit
29
3
7
Access &
Access &
Default
Default
000 b
010 b
010 b
R/W
R/W
R/W
R/W
0 b
Reserved
Initialization Complete (IC): This bit is used for communication of software
state between the memory controller and the BIOS. BIOS sets this bit to 1 after
initialization of the DRAM memory array is complete.
Reserved
Refresh Mode Select (RMS): This field determines whether refresh is enabled
and, if so, at what rate refreshes will be executed.
Reserved
DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks
inserted between a row activate command and a read or write command to that
row.
Reserved
DRAM RAS Precharge (tRP). This bit controls the number of clocks that are
inserted between a row precharge command and an activate command to the
same rank.
000:Refresh disabled
001:Refresh enabled. Refresh interval 15.6 µsec
010:Refresh enabled. Refresh interval 7.8 µsec
011:Refresh enabled. Refresh interval 3.9 µsec
100:Refresh enabled. Refresh interval 1.95 µsec
111:Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other:Reserved
MCHBAR
120-123h
4000280_00ss_h
R/W
32 bits
EncodingtRCD
000:2 DRAM Clocks
001:3 DRAM Clocks
010:4 DRAM Clocks
011:5 DRAM Clocks
100 - 111:Reserved
EncodingtRP
000:2 DRAM Clocks
001:3 DRAM Clocks
010:4 DRAM Clocks
011:5 DRAM Clocks
100 - 111:Reserved
Description
Description
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