NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 91

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Bit
8
7
6
5
4
3
2
1
0
Access &
Default
R/WO
R/W
R/W
R/W
R/W
0 b
0 b
RO
0 b
RO
0 b
RO
0 b
0 b
0 b
0 b
SERR Message Enable (SERRE1)
This bit is an enable bit for Device 1 SERR messaging. The MCH communicates the
SERRB condition by sending an SERR message to the ICH7. This bit, when set,
enables reporting of non-fatal and fatal errors to the Root Complex. Note that
errors are reported if enabled either through this bit or through the PCI Express
specific bits in the Device Control Register
0: The SERR message is generated by the MCH for Device 1 only under conditions
1: The MCH is enabled to generate SERR messages which will be sent to the ICH7
Parity Error Enable (PERRE)
Controls whether or not the Master Data Parity Error bit in the PCI Status register
can bet set.
0: Master Data Parity Error bit in PCI Status register cannot be set.
1: Master Data Parity Error bit in PCI Status register can be set.
VGA Palette Snoop
Not Applicable or Implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE)
Not Applicable or Implemented. Hardwired to 0.
Special Cycle Enable (SCE)
Not Applicable or Implemented. Hardwired to 0.
Bus Master Enable (BME): controls the ability of the PCI Express link port to
forward memory and I/O Read/Write requests in the upstream direction
0: This device is prevented from making memory or IO requests to its primary bus.
1: This device is allowed to issue requests to its primary bus. Completions for
This bit does not affect forwarding of Completions from the primary interface to the
secondary interface.
Memory Access Enable (MAE)
0: All of device 1’s memory space is disabled.
1: Enable the Memory and Pre-fetchable memory address ranges defined in the
I/O Access Enable (IOAE)
0: All of device 1’s I/O space is disabled.
1: Enable the I/O address range defined in the IOBASE1, and IOLIMIT1 registers.
Reserved
enabled individually through the Device Control Register.
for specific Device 1 error conditions generated/detected on the primary side of
the virtual PCI to PCI Express bridge (not those received by the secondary
side). The error status is reported in the PCISTS1 register.
Note that according to PCI Specification, as MSI interrupt messages are in-band
memory writes, disabling the bus master enable bit prevents this device from
generating MSI interrupt messages or passing them from its secondary bus to
its primary bus. Upstream memory writes/reads, IO writes/reads, peer writes/
reads, and MSIs will all be treated as invalid cycles. Writes are forwarded to
memory address 0 with byte enables de-asserted. Reads will be forwarded to
memory address 0 and will return Unsupported Request status (or Master
abort) in its completion packet.
previously issued memory read requests on the primary bus will be issued when
the data is available.
MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
Description
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