NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 61

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.1.25
4.1.26
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
PAM5—Programmable Attribute Map 5 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E0000h-0E7FFFh.
PAM6—Programmable Attribute Map 6 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E8000h-0EFFFFh.
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
Bit
Bit
Access &
Access &
Default
Default
00 b
00 b
00 b
00 b
R/W
R/W
R/W
R/W
Reserved
0E4000-0E7FFF Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E4000 to 0E7FFF.
Reserved
0E0000-0E3FFF Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E0000 to 0E3FFF.
Reserved
0EC000-0EFFFF Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E4000 to 0E7FFF.
Reserved
0E8000-0EBFFF Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E0000 to 0E3FFF.
0
95h
00h
R/W
8 bits
0
96h
00h
R/W
8 bits
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
00:DRAM Disabled: Accesses are directed to the DMI.
01:Read Only: All reads are serviced by DRAM. All writes are forwarded to the
10:Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
DMI.
DMI.
DMI.
DMI.
Description
Description
61