NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 66

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.1.33
66
TOM - Top of Memory
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This Register contains the size of physical memory. BIOS determines the memory size
reported to the OS using this Register.
15:9
2:1
8:0
Bit
Bit
3
0
Access &
Access &
Default
Default
R/W/L
R/W/L
R/W
01h
00 b
RO
1 b
0 b
Reserved
Top of Memory (TOM): This register reflects the total amount of populated
physical memory. This is also the amount of addressable physical memory when
remapping is used appropriate to ensure that no physical memory is wasted. This is
NOT necessarily the highest main memory address (holes may exist in main
memory address map due to addresses allocated for memory mapped I/O).
These bits correspond to address bits 35:27 (128 MB granularity). Bits 26:0 are
assumed to be 0.
L2 Cache Enable for SMRAM (SM_L2): This bit is forced to ‘1’ by the MCH.
TSEG Size (TSEG_SZ): This field selects the size of the TSEG memory block if
enabled. Memory from the top of DRAM space is partitioned away so that it may
only be accessed by the processor interface and only then when the SMM bit is set
in the request packet. Non-SMM accesses to this memory region are sent to the
DMI when the TSEG memory block is enabled.
Once D_LCK has been set, these bits become read only.
TSEG Enable (T_EN): This bit is the enabling of SMRAM memory for Extended
SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to
appear in the appropriate physical address space. Note that once D_LCK is set, this
bit becomes read only.
00:1-MB TSEG (TOLUD – 1M) to (TOLUD).
01:2-MB TSEG (TOLUD – 2M) to (TOLUD).
10:8-MB TSEG (TOLUD – 8M) to (TOLUD).
11:Reserved.
0
A0-A1h
0001h
RO; R/W;
16 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)
Description
Description