NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 107

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.34
5.1.35
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
PCI_EXPRESS_CAP—PCI Express Link Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express device capabilities.
DCAP—Device Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express link capabilities.
15:14
13:9
31:6
7:4
3:0
4:3
2:0
Bit
Bit
8
5
Access &
Access &
Default
Default
R/WO
000 b
00 h
00 b
1 b
4 h
1 h
0 b
RO
RO
RO
RO
RO
RO
Reserved
Interrupt Message Number
Not Applicable or Implemented. Hardwired to 0.
Slot Implemented
0: The PCI Express Link associated with this port is connected to an integrated
1: The PCI Express link associated with this port is connected to a slot.
BIOS must initialize this field appropriately if a slot connection is not implemented.
Device/Port Type
Hardwired to 0100b to indicate root port of PCI Express Root Complex.
PCI Express Capability Version
Hardwired to 1 as it is the first version.
Reserved
Extended Tag Field Supported
Hardwired to indicate support for 5-bit Tags as a Requestor.
Phantom Functions Supported
Not Applicable or Implemented. Hardwired to 0.
Max Payload Size
Hardwired to indicate 128B maximum supported payload for Transaction Layer
Packets (TLP).
component or is disabled.
1
A2h
0141h
RO; R/WO
16 bits
1
A4h
00000000h
RO
32 bits
Description
Description
107