NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 169

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Functional Description
9.3.4.1
9.3.4.2
9.3.5
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Dual PCI Express Indication
Secondary Slot (PCIE1) PRSNT2# is connected to DPEN# to indicate whether a PCI
Express card is present in the secondary slot and therefore Dual PCI Express operation
is desired. DPEN#=0 means PCI Express card is present in secondary slot.
When the DPEN# strap is pulled low by a PCI Express card in the secondary slot, the
Device 3 Enable configuration bit = 1 (enabled) out of reset. When the DPEN# strap is
not pulled low, the Device 3 Enable configuration bit = 0 (disabled) out of reset.
When the Device 3 enable = 0 (disabled), the clock to the send 2
will be gated.
Primary Slot Device Present Indication
Primary Slot (PCIE0) PRSNT2# is connected to PRIPRSNT# to indicate whether a PCI
Express card is present in the primary slot. PRIPRSNTB=0 means PCI Express card is
present in primary slot.
Peer-to-Peer
No peer-to-peer reads are required nor supported.
Peer-to-peer writes are supported from DMI to both PCIE0 and PCIE1. This is via the
“central” peer path that existed in past products. This central peer path is also capable
of PCIE0 and PCIE1 writes to DMI (non-POR feature) and as a backup option for PCIE0
to PCIE1 performance peer writes.
Peer-to-peer writes are supported in both directions between PCIE0 and PCIE1 via the
new “performance” peer path. 36 bit addressing is supported on the performance peer
path. Relaxed ordering must be disabled when using the performance peer path.
The MCH has an in/out dependency when peer traffic is involved. This is a violation of
the PCI 2.3 spec. To prevent potential lockup in the system the MCH requires that the
devices attached to the root ports involved be PCI 2.3 compliant (so the devices are
known to not have this in/out dependency).
Peer-to-peer writes through the performance peer path ignore the D state of both of
the MCH PCI Express ports. Software that follows the PCI Power Management
specification should not allow for such upstream/peer cycles to occur, but if they do
they will flow through the MCH as if in the D0 state. Peer-to-peer writes through the
central peer path would be an unsupported request on the primary side of a PCI
Express port virtual bridge if in a non-D0 state.
If the performance peer path is enabled and a write occurs to that range (appropriate
device defined memory and prefetchable memory ranges) then the central peer path
state (enabled/disabled) is a don’t care. If the performance peer path is disabled and a
write occurs to that range then the central peer path state controls whether that write
will be completed to the intended device (enabled) or the write becomes unsupported
(disabled).
nd
PCI Express port
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