NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 123

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.60
5.1.61
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
LE1A—Link Entry 1 Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Second part of a Link Entry, which declares an internal link to another Root Complex
Element.
LE2D—Link Entry 2 Description (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
First part of a Link Entry, which declares an internal link to another Root Complex
Element.
63:32
31:12
31:24
23:16
15:2
11:0
Bit
Bit
Bit
1
0
Access &
Access &
Default
Default
Access &
0 0000 h
R/WO
Default
R/WO
00 h
00 h
R/WO
0 b
0 b
RO
RO
Reserved
Link Type
Indicates that the link points to memory-mapped space (for RCRB). The link address
specifies the 64-bit base address of the target RCRB.
Link Valid
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
Target Port Number
Specifies the port number associated with the element targeted by this link entry
(PCIE1). The target port number is with respect to the component that contains this
element as specified by the target component ID.
Target Component ID
Identifies the physical or logical component that is targeted by this link entry. A
value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Reserved
Link Address
Memory mapped base address of the RCRB that is the target element (Egress
Port) for this link entry.
Reserved
1
158h
0000000000000000h
R/WO
64 bits
1
160h
00000002h
RO, R/WO
32 bits
Description
Description
Description
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