NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 57

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.1.18
4.1.19
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
DERRSYN - DRAM Error Syndrome (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register is used to report the ECC syndromes for each quadword of a 32B-aligned
data quantity read from the DRAM array.
DERRDST - DRAM Error Destination (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register is used to report the destination of the data containing an ECC error
whose address is recorded in DEAP.
7:0
7:6
5:0
Bit
Bit
Access &
Access &
00 0000b
Default
Default
RO/S
RO/S
DRAM ECC Syndrome (DECCSYN): After a DRAM ECC error on any QWord of
the data chunk resulting from a read command, hardware loads this field with a
syndrome that describes the set of bits associated with the first QWord containing
an error. Note that this field is locked from the time that it is loaded up to the time
when the error flag is cleared by software. If the first error was a single bit,
correctable error, then a subsequent multiple bit error on any of the QWords in
this read transaction or any subsequent read transaction will cause the field to be
re-recorded. When a multiple bit error is recorded, then the field is locked until
the error flag is cleared by software. In all other cases, an error, which occurs
after the first error, and before the error flag, has been cleared by software, will
escape recording.
These bits are reset on PWROK.
Reserved
ECC Error Source Code (EESC): This field is updated concurrently with
DERRSYN.
Intel® 3000 chipset only:
Intel® 3010 chipset only:
0
5Ch
00h
RO/S;
8 bits
0
5Dh
00h
RO/S;
8 bits
00h:
01h - 07h: Reserved
08h - 09h: DMI VC0 initiated and targeting cycles/data
0Ah - 0Bh: DMI VC1 initiated and targeting cycles/data
0Ch:
0Dh - 0Fh: Reserved
10h:
11h:
12h:
13h:
14h - 15h: (Primary) PCI Express initiated and targeting cycles/data
16h - 3Fh: Reserved
16h - 1Fh: Reserved
20h:
21h:
22h:
23h:
24h - 25h: Secondary PCI Express initiated and targeting cycles/data
26h - 3Fh: Reserved
Processor to memory reads
DMI VCp initiated and targeting cycles/data
(Primary) PCI Express initiated and targeting cycles/data
Reserved
(Primary) PCI Express initiated and targeting cycles/data
Reserved
Secondary PCI Express initiated and targeting cycles/data
Reserved
Secondary PCI Express initiated and targeting cycles/data
Reserved
Description
Description
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