NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 94

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.8
5.1.9
5.1.10
94
HDR1—Header Type (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical
register exists at this location.
PBUSN1—Primary Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI
bus 0.
SBUSN1—Secondary Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies the bus number assigned to the second bus side of the “virtual”
bridge i.e. to PCI Express link. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express link.
7:0
7:0
7:0
Bit
Bit
Bit
Access &
Access &
Access &
Default
Default
Default
01 h
00 h
00 h
R/W
RO
RO
Header Type Register (HDR)
Returns 01 to indicate that this is a single function device with bridge header layout.
Primary Bus Number (BUSN)
Configuration software typically programs this field with the number of the bus on
the primary side of the bridge. Since device 1 is an internal device and its primary
bus is always 0, these bits are read only and are hardwired to 0.
Secondary Bus Number (BUSN)
This field is programmed by configuration software with the bus number assigned to
PCI Express link.
1
0Eh
01h
RO
8 bits
1
18h
00h
RO
8 bits
1
19h
00h
RO
8 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Host-PCI Express Bridge Registers (D1:F0)