NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 167

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Functional Description
Table 9-6.
9.3.3
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Lane Mapping Configurations (Sheet 2 of 2)
Device 1 must be enabled any time any PCI Express device is present (regardless of
slot). Device 3 has a separate clock tree from Device 1 which will be gated based on
the Device 3 enable configuration bit (PCIE1 disabled=gated PCIE1 clk).
Lane Reversal
Device 1 registers are always associated with the control of the primary slot (PCIE0).
Device 3 registers are always associated with the control of the secondary slot (PCIE1).
When lane reversal is indicated to the MCH, all 16 lanes of the two PCI Express ports
are reversed end-to-end. As shown in the following figure, the device controls
associated with the lanes also changes such that the same logical lanes are always
controlled by the same device.
Dual PCI Express
No PCI Express
Config Name
Primary Slot
x1, x4, x8
None
(PCIE0)
x1, x4, x8
None
Secondary
(PCIE1)
Slot
Primary
(PCIE0)
Prim ary
em pty
(PC IE0)
x8
PRSNT1#
PRSNT2#
PRS NT1#
PRS NT2#
Example Figures
Secondary
Secondary
(PCIE1)
empty
(PCIE1)
x8
PRSNT1#
PRSNT2#
PRS NT1#
PRS NT2#
DPEN#
0
7
0
7
DP EN# P RIPRS NT#
0
7
0
7
0
1
Dev 3
Dev 1
PRIPRSNT#
MCH
MC H
0
1
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