NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 37

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

MCH Register Description
Table 3-1.
3.3
3.3.1
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Device Number Assignment for Internal MCH Devices
Configuration Mechanism
The processor is the originator of configuration cycles so the FSB is the only interface in
the platform where these mechanisms are used. The MCH translates transactions
received through both configuration mechanisms to the same format.
Standard PCI Configuration Mechanism
The following is the mechanism for translating processor I/O bus cycles to configuration
cycles.
The PCI Specification defines a slot based “configuration space” that allows each device
to contain up to 8 functions with each function containing up to 256 8-bit configuration
registers. The PCI specification defines two bus cycles to access the PCI configuration
space: Configuration Read and Configuration Write. Memory and I/O spaces are
supported directly by the CPU. Configuration space is supported by a mapping
mechanism implemented within the MCH.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at
I/O address 0CF8h through 0CFBh) and the CONFIG_DATA Register (at I/O address
0CFCh through 0CFFh). To reference a configuration register a DWord I/O write cycle is
used to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on
that bus, the function within the device, and a specific configuration register of the
device function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a
configuration cycle. CONFIG_DATA then becomes a window into the four bytes of
configuration space specified by the contents of CONFIG_ADDRESS. Any read or write
to CONFIG_DATA will result in the MCH translating the CONFIG_ADDRESS into the
appropriate configuration cycle.
The MCH is responsible for translating and routing the CPU’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration
registers, DMI or PCI Express.
Host Bridge / DRAM Controller
Host-to-PCI Express Bridge (virtual P2P)
MCH Function
Device 1 and 3
Device#
Device 0
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