NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 73

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.2.2
4.2.3
4.2.4
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
In all modes, if a DIMM is single sided, it appears as a populated rank and an empty
rank. A DRB must be programmed appropriately for each.
Each Rank is represented by a byte. Each byte has the following format.
C0DRB1—Channel A DRAM Rank Boundary Address 1
MMIO Range:
Address Offset:
Default:
Access:
Size:
The operation of this register is detailed in the description for register C0DRB0.
C0DRB2—Channel A DRAM Rank Boundary Address 2
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRB0.
C0DRB3—Channel A DRAM Rank Boundary Address 3
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRB0.
7:0
Bit
Access &
Default
00 h
R/W
Channel A DRAM Rank Boundary Address: This 8 bit value defines the upper
and lower addresses for each DRAM rank. Bits 6:2 are compared against Address
31:27 to determine the upper address limit of a particular rank. Bits 1:0 must be
0s. Bit 7 may be programmed to a ‘1’ in the highest DRB (DRB3) if 4 GBs of
memory is present.
MCHBAR
101h
00h
R/W
8 bits
MCHBAR
102h
00h
R/W
8 bits
MCHBAR
103h
00h
R/W
8 bits
Description
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