NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 103

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.26
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
PM_CS1—Power Management Control/Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
18:16
31:16
14:13
15:8
12:9
7:0
7:2
1:0
Bit
Bit
15
8
Access &
90h / A0h
Access &
Default
Default
R/W/S
010 b
01 h
00 b
00 b
R/W
0 h
RO
RO
RO
RO
0 b
RO
RO
0 b
Reserved
PCI PM CAP Version
Hardwired to 02h to indicate there are 4 bytes of power management registers
implemented and that this device complies with revision 1.1 of the PCI Power
Management Interface Specification.
Pointer to Next Capability
This contains a pointer to the next item in the capabilities list. If MSICH (CAPL[0] @
7Fh) is 0, then the next item in the capabilities list is the Message Signaled
Interrupts (MSI) capability at 90h. If MSICH (CAPL[0] @ 7Fh) is 1, then the next
item in the capabilities list is the PCI Express capability at A0h.
Capability ID
Value of 01h identifies this linked list item (capability structure) as being for PCI
Power Management registers.
PME Status
Indicates that this device does not support PMEB generation from D3
Data Scale
Indicates that this device does not support the power management data register.
Data Select
Indicates that this device does not support the power management data register.
PME Enable
Indicates that this device does not generate PMEB assertion from any D-state.
0: PMEB generation not possible from any D State
1: PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
Reserved
Power State
Indicates the current power state of this device and can be used to set the device
into a new power state. If software attempts to write an unsupported state to this
field, write operation must complete normally on the bus, but the data is discarded
and no state change occurs.
00: D0
01: D1 (Not supported in this device.)
10: D2 (Not supported in this device.)
11: D3
Support of D3
While in the D3
transactions (for power management control). This device also cannot generate
interrupts or respond to MMR cycles in the D3 state. The device must return to the
D0 state in order to be fully functional.
There is no hardware functionality required to support these Power States.
1
84h
00000000h
RO, R/W
32 bits
cold
hot
does not require any special action.
state, this device can only act as the target of PCI configuration
Description
Description
cold
.
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