NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 23

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Signal Description
2.1
Note:
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Interface Signals
Unless otherwise noted, the voltage level for all signals in this interface is tied to the
termination voltage of the Host Bus (V
HADS#
HBNR#
HBPRI#
HBREQ0#
HCPURST#
HDBSY#
HDEFER#
HDINV[3:0]#
HDRDY#
HEDRDY#
HA[35:3]#
HADSTB[1:0]#
Signal Name
Type
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
GTL+
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
Address Strobe: The CPU bus owner asserts HADS# to indicate the first of
two cycles of a request phase. The MCH can assert this signal for snoop cycles
and interrupt messages.
Block Next Request: This signal is used to block the current request bus
owner from issuing new requests. This signal is used to dynamically control
the CPU bus pipeline depth.
Priority Agent Bus Request: The MCH is the only Priority Agent on the CPU
bus. It asserts this signal to obtain the ownership of the address bus. This
signal has priority over symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the HLOCK# signal
was asserted.
Bus Request 0: The MCH pulls the processor’s bus HBREQ0# signal low
during HCPURST#. The processor samples this signal on the active-to-inactive
transition of HCPURST#. The minimum setup time for this signal is 4 HCLKs.
The minimum hold time is 2 HCLKs and the maximum hold time is 20 HCLKs.
HBREQ0# should be tristated after the hold time requirement has been
satisfied.
CPU Reset: The HCPURST# pin is an output from the MCH. The MCH asserts
HCPURST# while RSTIN# is asserted and for approximately 1 ms after
RSTIN# is de-asserted. The HCPURST# allows the CPUs to begin execution in
a known state.
Note that the ICH7 must provide CPU frequency select strap setup and hold
times around HCPURST#. This requires strict synchronization between MCH
HCPURST# de-assertion and the ICH7 driving the straps.
Data Bus Busy: This signal is used by the data bus owner to hold the data
bus for transfers requiring more than one cycle.
Defer: Signals that the MCH will terminate the transaction currently being
snooped with either a deferred response or with a retry response.
Dynamic Bus Inversion: Driven along with the HD[63:0] signals,
HDINV[3:0]# indicate if the associated signals are inverted or not.
HDINV[3:0]# are asserted such that the number of data bits driven
electrically low (low voltage) within the corresponding 16 bit group never
exceeds 8.
Data Ready: This signal is asserted for each cycle that data is transferred.
Early Data Ready: This signal indicates that the data phase of a read
transaction will start on the bus exactly one common clock after assertion.
Host Address Bus: HA[35:3]# connect to the CPU address bus. During CPU
cycles, the HA[35:3]# are inputs. The MCH drives HA[35:3]# during snoop
cycles on behalf of DMI and PCI Express initiators. HA[35:3]# are transferred
at 2x rate.
Host Address Strobe: This signal is the source synchronous strobes used to
transfer HA[31:3]# and HREQ[4:0] at the 2x transfer rate.
HDINV[x]#
HDINV[3]#
HDINV[2]#
HDINV[1]#
HDINV[0]#
TT
).
Description
HD[63:48]#
HD[47:32]#
HD[31:16]#
HD[15:0]#
Data Bits
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