NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 67

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host Bridge Registers (Device 0, Function 0)
4.1.34
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
ERRSTS—Error Status (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register is used to report various error conditions via the SERR DMI messaging
mechanism. A SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set
regardless of whether or not the SERR is enabled and generated. After the error
processing is complete, the error logging mechanism can be unlocked by clearing the
appropriate status bit by software writing a '1' to it.
15:12
7:2
Bit
11
10
9
8
1
0
Access &
Default
R/WC/S
R/WC/S
R/WC/S
R/WC/S
R/WC/S
0 b
0 b
0 b
0 b
0 b
Reserved
MCH Thermal Sensor Event for SMI/SCI/SERR:
This bit indicates that a MCH Thermal Sensor trip has occurred and an SMI, SCI or
SERR has been generated. The status bit is set only if a message is sent based on
Thermal event enables in Error command, SMI command and SCI command
registers. A trip point can generate one of SMI, SCI, or SERR interrupts (two or
more per event is invalid). Multiple trip points can generate the same interrupt, if
software chooses this mode, subsequent trips may be lost. If this bit is already
set, then an interrupt message will not be sent on a new thermal sensor event.
Reserved
LOCK to non-DRAM Memory Flag (LCKF): When this bit is set to 1, the MCH
has detected a lock operation to memory space that did not map into DRAM.
Received Refresh Timeout Flag (RRTOF):
This bit is set when 1024 memory core refreshes are enqueued.
Reserved
Multiple-bit DRAM ECC Error Flag (DMERR): If this bit is set to 1, a memory
read data transfer had an uncorrectable multiple-bit error. When this bit is set, the
address, channel number, and device number that caused the error are logged in
the DEAP register. Once this bit is set the DEAP, DERRSYN, and DERRDST fields
are locked until the CPU clears this bit by writing a 1. Software uses bits [1:0] to
detect whether the logged error address is for Single or Multiple-bit error. This bit
is reset on PWROK.
Single-bit DRAM ECC Error Flag (DSERR): If this bit is set to 1, a memory
read data transfer had a single-bit correctable error and the corrected data was
sent for the access. When this bit is set the address and device number that
caused the error are logged in the DEAP register. Once this bit is set the DEAP,
DERRSYN, and DERRDST fields are locked to further single bit error updates until
the CPU clears this bit by writing a 1. A multiple bit error that occurs after this bit
is set will overwrite the DEAP and DERRSYN fields with the multiple-bit error
signature and the DMERR bit will also be set. A single bit error that occurs after a
multibit error will set this bit but will not overwrite the other fields. This bit is
reset on PWROK.
0
C8-C9h
0000h
R/WC/S, RO
16 bits
Description
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