NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 80

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

4.2.18
4.2.19
4.2.20
4.2.21
4.2.22
80
C1DCLKDIS—Channel B DRAM Clock Disable
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DCLKDIS.
C1BNKARC—Channel B Bank Architecture
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0BNKARC.
C1DRT1—Channel 1 DRAM Timing Register 1
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRT1.
C1DRC0—Channel 1 DRAM Controller Mode 0
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRC0.
C1DRC1—Channel 1 DRAM Controller Mode 1
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRC1.
MCHBAR
18Ch
00h
R/W/L
8 bits
MCHBAR
18E-18Fh
0000h
R/W
16 bits
MCHBAR
194-197h
02483D22h
R/W
32 bits
MCHBAR
1A0-1A3h
4000280_00ssh
R/W
32 bits
MCHBAR
1A4-1A7h
00000000h
R/W, R/W/L
32 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host Bridge Registers (Device 0, Function 0)