NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 137

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Direct Media Interface (DMI) RCRB
7.1.3
7.1.4
7.1.5
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
DMIPVCCAP2—DMI Port VC Capability Register 2
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
Describes the configuration of Virtual Channels associated with this port.
DMIPVCCTL—DMI Port VC Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIVC0RCAP—DMI VC0 Resource Capability
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
31:24
31:23
22:16
23:8
15:4
14:8
7:0
3:1
7:0
Bit
Bit
Bit
15
0
Access &
Access &
Access &
Default
Default
Default
000 b
00 h
01 h
R/W
00 h
01 h
0 b
RO
RO
RO
RO
RO
VC Arbitration Table Offset (ATO)
Indicates that no table is present for VC arbitration since it is fixed.
Reserved
VC Arbitration Capability
Indicates that the VC arbitration is fixed in the root complex. VC1 is highest priority
and VC0 is lowest priority.
Reserved
VC Arbitration Select
Indicates which VC should be programmed in the VC arbitration table. The root
complex takes no action on the setting of this field since there is no arbitration table.
Reserved
Reserved
Maximum Time Slots (MTS)
This VC implements fixed arbitration, and therefore this field is not used.
Reject Snoop Transactions (RTS)
This VC must be able to take snoopable transactions.
Reserved
Port Arbitration Capability (PAC)
Indicates that this VC uses fixed port arbitration.
DMIBAR
008h
00000001h
RO
32 bits
DMIBAR
00Ch
0000h
RO
16 bits
DMIBAR
010h
00000001h
RO
32 bits
Description
Description
Description
137