NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 29

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NH82801GR S L8FY

Manufacturer Part Number
NH82801GR S L8FY
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801GR S L8FY

Lead Free Status / RoHS Status
Compliant
Signal Description
2.8
2.9
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Power, Ground
Reset States and Pull-up/Pull-downs
This section describes the expected states of the MCH I/O buffers during and
immediately after the assertion of RSTIN#. This table only refers to the contributions
on the interface from the MCH and does NOT reflect any external influence (such as
external pull-up/pull-down resistors or external drivers).
DRIVE:
TERM:
LV:
HV:
IN:
TRI:
PU:
PD:
CMCT:
STRAP:
VCC
VTT
VCC_EXP
VCCSM
VCCA_3GBG
VCC2
VCCA_EXPPLL
VCCA_HPLL
VCCA_SMPLL
VSS
Name
Strong drive (to normal value supplied by core logic if not otherwise
stated)
Normal termination devices are turned on
Low voltage
High voltage
Input buffer enabled
Tri-state
Weak internal pull-up: 7.2 KΩ - 11.1 KΩ, unless otherwise specified
Weak internal pull-down: 600 Ω - 880 Ω unless otherwise specified
Common Mode Center Tapped. Differential signals are weakly driven to
the common mode central voltage.
Strap input sampled on the asserting edge of PWROK.
Voltage
1.5 V
1.2 V
1.5 V
1.8 V
2.5 V
2.5 V
1.5 V
1.5 V
1.5 V
0 V
Core Power
Processor System Bus Termination Power
PCI Express and DMI Power
System Memory Power
PCI Express and DMI Analog Bandgap
2.5 V CMOS Power
PCI Express PLL Analog Power
Host PLL Analog Power
System Memory PLL Analog Power
Ground
Description
29

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