NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 124

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.62
5.1.63
124
LE2A—Link Entry 2 Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Second part of a Link Entry, which declares an internal link to another Root Complex
Element.
UESTS—Uncorrectable Error Status (D1:F0)
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Reports error status of individual error sources on a PCI Express device. An individual
error status bit that is set indicates that a particular error occurred. Software may clear
an error status by writing a 1 to the respective bit.
63:20
19:15
31:21
15:2
14:0
Bit
Bit
Bit
20
19
18
17
16
15
1
0
Access &
Default
Access &
Access &
0 0011 b
R/WO
Default
Default
R/WC/S
R/WC/S
R/WC/S
R/WC/S
RO
1 b
0 b
0 b
0 b
0 b
0 b
RO
Reserved
Link Type
Indicates that the link points to configuration space of an integrated device.
The link address specifies the configuration address (segment, bus, device, function)
of the target root port.
Link Valid
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
Reserved
Device Number
Target for this link is PCIE1 (Device 3)
Reserved
Reserved
Unsupported Request Error Status
Reserved
Malformed TLP Status
Receiver Overflow Status
Unexpected Completion Status
Reserved
1
168h
0000000000018000h
R/O
64 bits
0/1/0/MMR
1C4-1C7h
00000000h
RO; R/WC/S
32 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Host-PCI Express Bridge Registers (D1:F0)
Description
Description