NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 38

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

3.3.2
Figure 3-3.
38
PCI Express
Located by
Address
Base
0xFFFFFFF
0x1FFFFF
0xFFFFF
PCI Express Enhanced Configuration Mechanism
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express
configuration space is divided into a PCI 2.3 compatible region, which consists of the
first 256 B of a logical device’s configuration space and a PCI Express extended region,
which consists of the remaining configuration space.
The PCI compatible region can be accessed using either the Standard PCI Configuration
Mechanism or the PCI Express Enhanced Configuration Mechanism described in this
section. The extended configuration registers may only be accessed using the PCI
Express enhanced configuration access mechanism. To maintain compatibility with PCI
configuration addressing mechanisms, system software must access the extended
configuration space using 32-bit operations (32-bit aligned) only. These 32-bit
operations include byte enables allowing only appropriate bytes within the Dword to be
accessed. Locked transactions to the PCI Express memory mapped configuration
address space are not supported. All changes made using either access mechanism are
equivalent.
The PCI Express Enhanced Configuration Mechanism utilizes a flat memory-mapped
address space to access device configuration registers. This address space is reported
by the system firmware to the operating system. There is a register, PCIEXBAR, that
defines the base address for the 256 MB block of addresses below top of addressable
memory (currently 8 GB) for the configuration space associated with all buses, devices
and functions that are potentially a part of the PCI Express root complex hierarchy.
PCIEXBAR register has controls to limit the size of this reserved memory mapped
space. 256 MB is the amount of address space required to reserve space for every bus,
device, and function that could possibly exist. Options for 128 MB and 64 MB exist in
order to free up those addresses for other uses. In these cases the number of buses
and all of their associated devices and functions are limited to 128 or 64 buses
respectively.
The PCI Express Configuration Transaction Header includes an additional 4 bits
(ExtendedRegisterAddress[3:0]) between the Function Number and Register Address
fields to provide indexing into the 4 KB of configuration space allocated to each
potential device. For PCI Compatible Configuration Requests, the Extended Register
Address field must be all zeros.
Memory Map to PCI Express Device Configuration Space
0
Bus 255
Bus 1
Bus 0
0xFFFFF
0xFFFF
0x7FFF
Device 31
Device 1
Device 0
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
0x7FFF
0x1FFF
0xFFF
Function 7
Function 1
Function 0
MCH Register Description
0xFFF
0xFF
0x3F
PCI Compatible
PCI Compatible
Configuration
PCI Express
Configuration
Space Header
Configuration
Extended
Space
Space