NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 161

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Functional Description
Figure 9-1.
9.2.1
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start in channel A and stay there until the end of the highest rank in channel
A, then addresses continue from the bottom of channel B to the top. Real world
applications are unlikely to make requests that alternate between addresses that sit on
opposite channels with this memory organization, so in most cases, bandwidth will be
limited to that of a single channel. The system designer is free to populate either
channel in any manner, including degenerating to single channel case.
System Memory Styles
System Memory Configuration Registers Overview
The configuration registers located in the PCI configuration space of the MCH control
the System Memory operation. Following is a brief description of configuration
registers.
DRAM Rank Boundary (CxDRBy): The x represents a channel, either A or B. The y
represents a rank, 0 through 3. DRB registers define the upper addresses for a rank of
DRAM devices in a channel. When the MCH is configured in asymmetric mode, each
register represents a single rank. When the MCH is configured in a dual interleaved
mode, each register represents a pair of corresponding ranks in opposing channels.
There are four DRB registers for each channel.
DRAM Rank Architecture (CxDRAy): The x represents a channel, either A or B. The
y represents a rank, 0 through 3. DRA registers specify the architecture features of
each rank of devices in a channel. The only architecture feature specified is page size.
When MCH is configured in asymmetric mode, each DRA represents a single rank in a
single channel. When MCH is configured in a dual-channel interleaved mode, each DRA
represents a pair of corresponding ranks in opposing channels. There are 4 DRA
registers per channel. Each requires only 3 bits, so there are two DRAs packed into a
byte.
DRAM Timing (CxDRT1): The x represents a channel, A or B represented by 0 and 1
respectively. The DRT register defines the timing parameters for all devices in a
channel. The BIOS programs this register with “least common denominator” values
after reading the SPD registers of each DIMM in the channel.
single channel
CHA or CHB
CL
TOM
0
scheme
XOR bit 6 => CL
channels don’t have to match
dual channel interleaved
CHB
CHA
CHB
CHA
CHB
CHA
CL
TOM
0
channels don’t have to match
dual channel asymmetric
CHB
CHA
CL
CHB -
TOM
CHB - 0
CHA -
TOM
CHA - 0
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