AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 945

IC MCU 64KB FLASH 144LQFP

AT32UC3A364-ALUT

Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A364-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A364-ALUT
Manufacturer:
Atmel
Quantity:
10 000
34.4.10.5
34.4.10.6
32072C–AVR32–2010/03
Error Reporting
Protected Reporting
The Service Access Bus may not be able to complete all accesses as requested. This may be
because the address is invalid, the addressed area is read-only or cannot handle byte/halfword
accesses, or because the chip is set in a protected mode where only limited accesses are
allowed.
The error bit is updated when an access completes, and is cleared when a new access starts.
What to do if the error bit is set:
A protected status may be reported during Shift-IR or Shift-DR. This indicates that the security
bit in the Flash Controller is set and that the chip is locked for access, according to
34.5.1.
The protected state is reported when:
What to do if the protected bit is set:
• During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat
• During Shift-DR of write data: The write data is ignored. The SAB stays in data mode. Repeat
• During Shift-IR: The new instruction is selected. The last operation performed using the old
• During Shift-DR of an address: The previous operation failed. The new address is accepted.
• During Shift-DR of read data: The read operation failed, and the read data is invalid.
• During Shift-DR of write data: The previous write operation failed. The new data is accepted
• While polling with CANCEL_ACCESS: The previous access was cancelled. It may or may not
• After power-up: The error bit is set after power up, but there has been no previous SAB
• The Flash Controller is under reset. This can be due to the AVR_RESET command or the
• The Flash Controller has not read the security bit from the flash yet (This will take a a few
• The security bit in the Flash Controller is set.
• Release all active AVR_RESET domains, if any.
• Release the RESET_N line.
• Wait a few ms for the security bit to clear. It can be set temporarily due to a reset.
• Perform a CHIP_ERASE to clear the security bit. NOTE : This will erase all the contents of the
scanning until the busy bit clears.
scanning until the busy bit clears.
instruction did not complete successfully.
If the read bit is set, a read operation is started.
and a write operation started. This should only occur during block writes or stream writes. No
error can occur between scanning a write address and the following write data.
have actually completed.
instruction so this error can be discarded.
RESET_N line.
ms). Happens after the Flash Controller reset has been released.
non-volatile memory.
AT32UC3A3/A4
Section
945

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